A Programmable CMOS Analog Vector Quantizer Chip

A Programmable CMOS Analog Vector Quantizer Chip

M.Sc. Thesis, 1999
Electronic and Communication Program
Instýtute of Science and Technology
Electric Electronic Faculty
Istanbul Technical University

Supervisor: Prof Dr. Uður Çilingiroðlu

Chip Layout (Jpg 415KB)

SUMMARY
A Programmable CMOS Analog Vector Quantizer Chip

In this thesis, a Vector Quantizer system is implemented with AMS 0.6mm CUQ CMOS double-poly double-metal technology. The Template-book (or code-book) of the system contains 64 Template-words (code-words). The template-word is constituted by 18 vector elements. The resolution of the vector elements is 6 bits. The template-book is fully programmable. Due to its programmability feature, system can be easily converted to a Kohonen's Self-Organizing Feature Map or a Space Partition Network. A novel distance cell (DCELL) that measures the Euclidean distances between the input vector and the template-words is proposed and analyzed in detail. Fully parallel architecture is used for computing the distances. A novel row amplifier is designed for biasing DCELLs. Lazzaro's WTA network is used for the selection process of the system. To change the RAM block content (template-book) a digital block is designed for interfacing with a microprocessor. Reading and writing operations of this interface block are asynchronous in order to facilitate communication with it. Proposed Vector Quantizer system occupies a silicon area of 4.1mm x 3.7mm (15.17mm2) including bonding pads.

Devrim Yýlmaz AKSIN
Electronic and Communication Engineer

Key Words : VLSI, Neural Network, Kohonen's Self-Organizing Feature Map, quantization, vector quantization, classification, Euclidean distance, winner-takes-all networks, switched-capacitors, coding, compression, image restoration, pattern recognition, speech recognition, texture classification, texture detection.

CONTENTS

REFERENCES

[1] Gray, Neuhoff, "Quantization", IEEE Transactions on Information Theory vol 44 No 6, pp 2325-2383, October 1998
[2] Tsu, Chang, Lee, "Structure Level Adaptation for Artificial Neural Networks", Kluwer Academic Pub. 1991.
[3] Linde, Buzo, Gray, "An algorithm for Vector Quantizer design", IEEE Transactions on Communication vol 28, pp 84-95 , January 1980
[4] Kim, Lee, "Discrete Cosine Transform-Classified Vector Quantization technique for image coding", Proceedings ICASSP'89, pp1831-1834
[5] Krishnamurthy, Ahalt, Melton, Chen, "Competitive learning algorithms for Vector Quantizer", IEEE Transactions on Neural Networks vol 3 No 3, pp 277-290, 1990
[6] Yair, Zeger, Gersho, "Competitive learning and soft competititon for Vector Quantizer design", IEEE Transactions on Signal Processing vol 40 No 2, February 1992
[7] Juang, Wong, Gray, "Distortion performance of Vector Quantizer for LPC voice coding", IEEE Transaction on Acoustic, Speech and Signal Processing vol 30(2), pp 294-304, April 1982.
[8] Makhoul, "Linear Prediction : A tutorial review", Proceedings of IEEE vol 63(4), pp 561-580, 1975
[9] Pedroni, Cauwenberghs, "A Low-Power CMOS Analog Vector Quantizer", IEEE Journal of Solid-State Circuits vol 32 No 8, pp 1278-1283, August 1997.
[10] Hochet, Peiris, Abdot, Declercq, "Implementation of a learning Kohonen neuron based on a new multilevel storage technique", IEEE Journal of Solid-State Circuits vol 26, pp 262-267, 1991
[11] Fang, Sheu, Chen, Choi, "A VLSI neural processor for image data-compression using self-organization networks", IEEE Transactions on Neural Networks vol 3 No 3, pp 506-518, 1992.
[12] He, Çilingiroðlu, "A charge-based on-chip adaptation Kohonen neural network", IEEE Transactions on Neural Networks vol 4 No 3, pp 462-469, 1993.
[13] Tuttle, Fallahi, Abidi, "An 8b CMOS vector A/D converter", in ISSCC tech Dig. Vol 36, pp 38-39, 1993.
[14] Pedroni, Cauwenberghs, "A charge-based CMOS parallel analog vector quantizer", in 'Advances in Neural Information Processing Systems' vol 7, pp 779-786, Cambridge , MA : MIT press 1989.
[15] Konda, Shibata, Ohmi, "Neuron-MOS correlator based on Manhattan distance computation for event recognition hardware", in Dig. Int. Symp. Circuits and Systems vol 4, pp 217-220, Atlanta 1996.
[16] He, Çilingiroðlu, Sanchez-Sinencio, "A high-Density and Low-Power Charge-Based Hamming Network", IEEE Transactions on Very Large Scale Integration (VLSI) Systems vol 1 No 1,pp 56-62, March 1993.
[17] Çilingiroðlu, "A Charge-Based Neural Hamming Classifier", IEEE Journal of Solid-State Circuits vol 28 No 1, pp 59-67, January 1993.
[18] Çilingiroðlu, Aksýn, "A 4-transistor Euclidean Distance Cell Fpr Analog Classifiers", Proceedings of ISCAS'98, Monterey 1998.
[19] Laker, Sansen, "Design of Analog Integrated Circuits and Systems", McGraw-Hill 1994
[20] TSIVIDIS, "The MOS transistor", McGraw-Hill 1988
[21] Geiger, Allen, Strader, "VLSI design technique for Analog and Digital circuits", McGraw-Hill 1990
[22] Antognetti, Massobrio, "Semiconductor Device Modelling with SPICE", McGraw-Hill 1988
[23] Arora, "MOSFET Models for VLSI Circuit Simulation", Springer-Verlag Wien New York, 1993
[24] Lakshmikumar, Hadaway, Copeland, " Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design", IEEE Journal of Solid-State Circuits vol sc-21 No 6, pp 1057-1066, December 1986.
[25] McCreary, "Matching properties and voltage and temperature dependence of MOS capacitors", IEEE Journal of Solid-State Circuits vol sc-16, pp 608-616, December 1981.
[26] Shyu, Temes, Yao, "Random error in MOS capacitors", IEEE Journal of Solid-State Circuits vol sc-17, pp 1070-1076, December 1982.
[27] Shyu, Temes, Krummenacher, "Random error effects in matched MOS capacitors and current sources", IEEE Journal of Solid-State Circuits vol sc-19, pp 948-955, December 1984.
[28] Papoulis, "Probability, Random variables and Stochastic Processes", Tokyo: McGraw-Hill, 1965
[29] Pelgrom, Duinmaijer, Welbers, "Matching Properties of MOS Transistors", IEEE Journal of Solid-State Circuits vol 24 No 5, pp 1433-1439, October 1989.
[30] Lovett, Welten, Mathewson, Mason, "Optimizing MOS Transistor Mismatch", IEEE Journal of Solid-State Circuits vol 33 No 1, pp 147-150, January 1998.
[31] Lazarro, Ryckebuch, Mahowald, Mead, "Winner-Take-All networks of O(N) complexity", in 'Advances in Neural Information Processing Systems 1', pp 703-711, San Mateo,CA:Morgan Kaufmann 1989.
[32] Wai-Chi Fang, Chi-Yung Chang, Bing J. Sheu, Oscal T.-C. Chen, John C. Curlander "VLSI Systolic Binary Tree Searched Vector Quantizer for Image Compression", IEEE Transactions on VLSI Systems, pp 33-34 March 1994.
[33] David Grant, John Taylor, Paul Houselander, "Design, Implementation and Evaluation of a High-Speed Integrated Hamming Neural Classifier", IEEE Journal of Solid-State Circuits, pp 1154-1157, Vol29 No9 September 1994
[34] Simon HAYKIN, "Neural Networks", Macmillan College Publishing Company 1994.
[35] Ichiro Fujimori, Tetsuro Sugimoto, "A 1.5V, 4.1mW Dual Channel Audio Delta-Sigma D/A Converter", IEEE Journal of Solid-State Circuits, pp 1863-1870, Vol33 No12, December 1994
[36] Private Communication with Barbaros ÞEKERKIRAN.
[37] Private Communication with Banu PAMÝR.

BACK