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| Content | : | Introduction to the CADENCE VLSI design environment. Examining the VLSI design flow. System level architectural design. VERILOG and VHDL hardware description languages (HDL). HDL codes for synthesis. Logic design and verification. Usage of VERILOG-XL environment. Automatic synthesis of logic design. Ambit BuildGates environment. Introduction to standard-cell libraries and their usage. Standard-cell placement & routing. Chip-level floorplanning, clock and power distribution. VLSI test methods and design for testability. FPGA&CPLD devices, Adders, Multipliers. | ||
| Links | : |
A guide to VHDL (PDF), by Burçin PAK Verilog Tutorial (PDF), by Erdoğan Özgür ATEŞ FPGAs & CPLDs (PDF), by Erdoğan Özgür ATEŞ Verilog Example 2(simple_alu.v) Verilog Signed Multiplication (Kombinezonsal) Verilog Signed Multiplication (Senkron) Ambit BuildGates Synthesis and Timing Verification Tutorial Ambit BuildGates Physical Synthesis Tutorial Ambit BuildGates Synthesis and Timing Tutorial |
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| Hours
Class |
: : |
10-13 Perşembe D5105 |
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