Books
[B1]
Yalçın, M.E., Ayhan, T., Yeniçeri, R.,
"Reconfigurable Cellular Neural Networks and Their Applications,"
SpringerBriefs in Applied Sciences and Technology,
Springer Nature, Switzerland, 2019, ISBN 978-3-030-17839-0.
@book{yenicerirB1,
author = {Yalcin, Mustak Erhan and Ayhan, Tuba and Yeniceri, Ramazan},
title = {{Reconfigurable Cellular Neural Networks and Their Applications}},
publisher = {Springer Cham},
year = {2019},
month = {April},
note = {{This book explores how neural networks can be designed to analyze sensory data in a way that mimics natural systems. It introduces readers to the cellular neural network (CNN) and formulates it to match the behavior of the Wilson–Cowan model. In turn, two properties that are vital in nature are added to the CNN to help it more accurately deliver mimetic behavior: randomness of connection, and the presence of different dynamics (excitatory and inhibitory) within the same network. It uses an ID matrix to determine the location of excitatory and inhibitory neurons, and to reconfigure the network to optimize its topology. The book demonstrates that reconfiguring a single-layer CNN is an easier and more flexible solution than the procedure required in a multilayer CNN, in which excitatory and inhibitory neurons are separate, and that the key CNN criteria of a spatially invariant template and local coupling are fulfilled. In closing, the application of the authors’ neuron population model as a feature extractor is exemplified using odor and electroencephalogram classification.}},
doi = {https://doi.org/10.1007/978-3-030-17840-6}}
author = {Yalcin, Mustak Erhan and Ayhan, Tuba and Yeniceri, Ramazan},
title = {{Reconfigurable Cellular Neural Networks and Their Applications}},
publisher = {Springer Cham},
year = {2019},
month = {April},
note = {{This book explores how neural networks can be designed to analyze sensory data in a way that mimics natural systems. It introduces readers to the cellular neural network (CNN) and formulates it to match the behavior of the Wilson–Cowan model. In turn, two properties that are vital in nature are added to the CNN to help it more accurately deliver mimetic behavior: randomness of connection, and the presence of different dynamics (excitatory and inhibitory) within the same network. It uses an ID matrix to determine the location of excitatory and inhibitory neurons, and to reconfigure the network to optimize its topology. The book demonstrates that reconfiguring a single-layer CNN is an easier and more flexible solution than the procedure required in a multilayer CNN, in which excitatory and inhibitory neurons are separate, and that the key CNN criteria of a spatially invariant template and local coupling are fulfilled. In closing, the application of the authors’ neuron population model as a feature extractor is exemplified using odor and electroencephalogram classification.}},
doi = {https://doi.org/10.1007/978-3-030-17840-6}}
Book Chapters
[C1]
Yeniçeri, R., Özoğuz, S., Yalçın, M.E.,
"A Chaotic Time-Delay Sampled-Data Systems with Applications,"
in Chapter 3 of New Research Trends in Nonlinear Circuits: Design, Chaotic Phenomena and Applications (Kyprianidis I., Stouboulos I. and Volos C. editors), Physics Research and Technology Series, pp.59-72, Nova Science Publishers, New York, 2014.
@inbook{yenicerirC1,
author = {Yeniceri, Ramazan and Ozoguz, Serdar and Yalcin, Mustak Erhan},
title = {{A Chaotic Time-Delay Sampled-Data Systems with Applications}},
booktitle = {{New Research Trends in Nonlinear Circuits : Design Chaotic Phenomena and Applications}},
year = {2014},
month = {August},
editor = {Volos, Christos K. and Kyprianidis, Ioannis and Stouboulos, Ioannis},
series = {{Electronics and Telecommunications Research}},
pages = {59-72},
chapter = {3},
publisher = {Nova Science Publishers, Inc.},
location = {New York},
isbn = {978-1-63321-406-4},
abstract = {The main implementation issues of chaotic circuits based on time-delay models are discussed and a sampled-data chaotic system is presented to address this issue. Detailed numerical simulations revealing system chaotic behavior are provided. In order to illustrate the usefulness of the chaotic circuit, the design of a high-performance true random bit generator is given. Test results verifying the proper operation of both the chaotic circuit and the random number generator are provided.},
url = {https://novapublishers.com/shop/new-research-trends-in-nonlinear-circuits-design-chaotic-phenomena-and-applications/}}
author = {Yeniceri, Ramazan and Ozoguz, Serdar and Yalcin, Mustak Erhan},
title = {{A Chaotic Time-Delay Sampled-Data Systems with Applications}},
booktitle = {{New Research Trends in Nonlinear Circuits : Design Chaotic Phenomena and Applications}},
year = {2014},
month = {August},
editor = {Volos, Christos K. and Kyprianidis, Ioannis and Stouboulos, Ioannis},
series = {{Electronics and Telecommunications Research}},
pages = {59-72},
chapter = {3},
publisher = {Nova Science Publishers, Inc.},
location = {New York},
isbn = {978-1-63321-406-4},
abstract = {The main implementation issues of chaotic circuits based on time-delay models are discussed and a sampled-data chaotic system is presented to address this issue. Detailed numerical simulations revealing system chaotic behavior are provided. In order to illustrate the usefulness of the chaotic circuit, the design of a high-performance true random bit generator is given. Test results verifying the proper operation of both the chaotic circuit and the random number generator are provided.},
url = {https://novapublishers.com/shop/new-research-trends-in-nonlinear-circuits-design-chaotic-phenomena-and-applications/}}
Journal Papers (SCI, SCI-E)
[J6]
Memiş, S., Yeniçeri R.,
"Model-based FPGA Implementation of A 6-DoF Dynamical Model Accelerator,"
IEEE Access, vol.12, pp.45279-45298, 2024.
@article{yenicerirJ6,
author = {Memis, Sezer and Yeniceri, Ramazan},
title = {{Model-Based FPGA Implementation of a 6-DoF Dynamical Model Accelerator}},
journal = {{IEEE Access}},
volume = {12},
number = {},
pages = {45279-45298},
year = {2024},
ISSN = {2169-3536},
keywords = {{Mathematical models; Computational modeling; Field programmable gate arrays; Hardware design languages; Hardware;6-DOF; Atmospheric modeling; 6-DoF; FPGA; model-based design; high-level synthesis; dynamics; quadrotor}},
abstract = {{The mathematical model of 6-DoF dynamics is used in different applications. In general, software-based solutions are utilized to implement the 6-DoF dynamic model. This paper introduces the FPGA-based implementation of the 6-DoF dynamics accelerator. The proposed hardware-based approach ensures the accuracy of the nonlinear model without compromising computational speed. The model-based approach and high-level synthesis have been employed in the design and implementation stages. Regarding design strategy, standard processor architecture, and resource-sharing methods have been applied to achieve FPGA resource efficiency. Seven datapath and finite state machines have been designed for seven different subsystems. The design resulted in hardware blocks that can execute all non-linear model equations 396 times in 1 ms using fixed/floating-point hybrid case and 434 times using pure fixed-point case. The model equations, which took an average of $\mathbf {0.4986}$ s to simulate in the Simulink environment, have been run on an FPGA in $\mathbf {7.1924}~\mu \text{s}$ . For seven design cases, numerical errors, resource utilization, and timing metrics are tabulated and presented to the reader.}},
doi = {https://doi.org/10.1109/ACCESS.2024.3381502}}
author = {Memis, Sezer and Yeniceri, Ramazan},
title = {{Model-Based FPGA Implementation of a 6-DoF Dynamical Model Accelerator}},
journal = {{IEEE Access}},
volume = {12},
number = {},
pages = {45279-45298},
year = {2024},
ISSN = {2169-3536},
keywords = {{Mathematical models; Computational modeling; Field programmable gate arrays; Hardware design languages; Hardware;6-DOF; Atmospheric modeling; 6-DoF; FPGA; model-based design; high-level synthesis; dynamics; quadrotor}},
abstract = {{The mathematical model of 6-DoF dynamics is used in different applications. In general, software-based solutions are utilized to implement the 6-DoF dynamic model. This paper introduces the FPGA-based implementation of the 6-DoF dynamics accelerator. The proposed hardware-based approach ensures the accuracy of the nonlinear model without compromising computational speed. The model-based approach and high-level synthesis have been employed in the design and implementation stages. Regarding design strategy, standard processor architecture, and resource-sharing methods have been applied to achieve FPGA resource efficiency. Seven datapath and finite state machines have been designed for seven different subsystems. The design resulted in hardware blocks that can execute all non-linear model equations 396 times in 1 ms using fixed/floating-point hybrid case and 434 times using pure fixed-point case. The model equations, which took an average of $\mathbf {0.4986}$ s to simulate in the Simulink environment, have been run on an FPGA in $\mathbf {7.1924}~\mu \text{s}$ . For seven design cases, numerical errors, resource utilization, and timing metrics are tabulated and presented to the reader.}},
doi = {https://doi.org/10.1109/ACCESS.2024.3381502}}
[J5]
Yeniçeri, R., Yalçın, M.E.,
"Multi-scroll chaotic attractors from a generalized time-delay sampled-data system,"
International Journal of Circuit Theory and Applications, vol.44, no.6, 2015.
@article{yenicerirJ5,
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {Multi-scroll chaotic attractors from a generalized time-delay sampled-data system},
journal = {{International Journal of Circuit Theory and Applications}},
volume = {44},
number = {6},
pages = {1263-1276},
year = {2016},
keywords = {chaos, multi-scroll, chaotic attractor, delay, delay line, priority encoder, {FPGA}},
abstract = {{Summary In this paper, the first generalization for time-delay sampled-data chaotic system in order to generate multi-scroll attractor is introduced with its circuit implementation. An efficient delay-line with binary priority encoding, parallel shifting, and binary decoding is also suggested and implemented to overcome the delay line realization drawback in such systems. The proposed system enhances the complexity of chaotic behavior by means of multi-scroll feature and exemplifies the simplification of chaotic systems for better realizations.}},
doi = {https://doi.org/10.1002/cta.2160}}
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {Multi-scroll chaotic attractors from a generalized time-delay sampled-data system},
journal = {{International Journal of Circuit Theory and Applications}},
volume = {44},
number = {6},
pages = {1263-1276},
year = {2016},
keywords = {chaos, multi-scroll, chaotic attractor, delay, delay line, priority encoder, {FPGA}},
abstract = {{Summary In this paper, the first generalization for time-delay sampled-data chaotic system in order to generate multi-scroll attractor is introduced with its circuit implementation. An efficient delay-line with binary priority encoding, parallel shifting, and binary decoding is also suggested and implemented to overcome the delay line realization drawback in such systems. The proposed system enhances the complexity of chaotic behavior by means of multi-scroll feature and exemplifies the simplification of chaotic systems for better realizations.}},
doi = {https://doi.org/10.1002/cta.2160}}
[J4]
Yeniçeri, R., Yalçın, M.E.,
"Asynchronous delay doubler and binary low-pass filter for a time-delay chaotic circuit,"
International Journal of Circuit Theory and Applications, vol.44, no.6, 2015.
@article{yenicerirJ4,
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {Asynchronous delay doubler and binary low-pass filter for a time-delay chaotic circuit},
journal = {{International Journal of Circuit Theory and Applications}},
volume = {44},
number = {6},
pages = {1211-1221},
year = {2016},
keywords = {delay, asynchronous, delay line, chaos, {FPGA}},
abstract = {{Summary In this paper, an asynchronous digital circuit is introduced for increasing the amount of delay in binary delay lines in an area efficient way. The circuit that uses its slave delay line twice per delay event is called asynchronous delay doubler (ADD). The delay increases exponentially, while the number of components increases linearly in the recursive utilization of ADD. An assumption on the event interval of the input 2signal helps to design the ADD in a very simple form. Therefore, the ADD can be implemented with a small amount of logical resource (gates or look-up tables). For proper operation, interval between the events (positive edge or negative edge) on the binary input signal should be larger than the delay provided by the recursive ADD block. In order to satisfy this assumption, an auxiliary asynchronous circuit, which is called binary low-pass filter (BLPF), is also proposed. The BLPF filters out the pulses narrower than the delay generated by its recursive ADD block. The proposed ADD design is suitable especially for the applications, like random number generation, in which the deviation in amount of delay is useful as an entropy source. In order to prove the concept, a chain of recursive ADD block is implemented with BLPFs on a field-programmable gate array and utilized in a true random bit generator.}},
doi = {https://doi.org/10.1142/S0218127415500212}}
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {Asynchronous delay doubler and binary low-pass filter for a time-delay chaotic circuit},
journal = {{International Journal of Circuit Theory and Applications}},
volume = {44},
number = {6},
pages = {1211-1221},
year = {2016},
keywords = {delay, asynchronous, delay line, chaos, {FPGA}},
abstract = {{Summary In this paper, an asynchronous digital circuit is introduced for increasing the amount of delay in binary delay lines in an area efficient way. The circuit that uses its slave delay line twice per delay event is called asynchronous delay doubler (ADD). The delay increases exponentially, while the number of components increases linearly in the recursive utilization of ADD. An assumption on the event interval of the input 2signal helps to design the ADD in a very simple form. Therefore, the ADD can be implemented with a small amount of logical resource (gates or look-up tables). For proper operation, interval between the events (positive edge or negative edge) on the binary input signal should be larger than the delay provided by the recursive ADD block. In order to satisfy this assumption, an auxiliary asynchronous circuit, which is called binary low-pass filter (BLPF), is also proposed. The BLPF filters out the pulses narrower than the delay generated by its recursive ADD block. The proposed ADD design is suitable especially for the applications, like random number generation, in which the deviation in amount of delay is useful as an entropy source. In order to prove the concept, a chain of recursive ADD block is implemented with BLPFs on a field-programmable gate array and utilized in a true random bit generator.}},
doi = {https://doi.org/10.1142/S0218127415500212}}
[J3]
Yeniçeri, R., Kılınç, S., Yalçın, M.E.,
"Attack on A Chaos-based Random Number Generator Using Anticipating Synchronization,"
International Journal of Bifurcation and Chaos, vol.25, no.2, 2015.
@article{yenicerirJ3,
author = {Yeniceri, Ramazan and Kilinc, Selcuk and Yalcin, Mustak Erhan},
title = {{Attack on a Chaos-Based Random Number Generator Using Anticipating Synchronization}},
journal = {{International Journal of Bifurcation and Chaos}},
volume = {25},
number = {02},
pages = {1550021},
year = {2015},
keywords = {chaos, random number generation, anticipating synchronization, physical attack},
abstract = {{Chaotic systems have been used in random number generation, owing to the property of sensitive dependence on initial conditions and hence the possibility to produce unpredictable signals. Within the types of chaotic systems, those which are defined by only one delay-differential equation are attractive due to their simple model. On the other hand, it is possible to synchronize to the future states of a time-delay chaotic system by anticipating synchronization. Therefore, random number generator (RNG), which employs such a system, might not be immune to the attacks. In this paper, attack on a chaos-based random number generator using anticipating synchronization is investigated. The considered time-delay chaotic system produces binary signals, which can directly be used as a source of RNG. Anticipating synchronization is obtained by incorporating other systems appropriately coupled to the original one. Quantification of synchronization is given by the bit error between the streams produced by the original and coupled systems. It is shown that the bit streams generated by the original system can be anticipated by the coupled systems beforehand.}},
doi = {https://doi.org/10.1142/S0218127415500212}}
author = {Yeniceri, Ramazan and Kilinc, Selcuk and Yalcin, Mustak Erhan},
title = {{Attack on a Chaos-Based Random Number Generator Using Anticipating Synchronization}},
journal = {{International Journal of Bifurcation and Chaos}},
volume = {25},
number = {02},
pages = {1550021},
year = {2015},
keywords = {chaos, random number generation, anticipating synchronization, physical attack},
abstract = {{Chaotic systems have been used in random number generation, owing to the property of sensitive dependence on initial conditions and hence the possibility to produce unpredictable signals. Within the types of chaotic systems, those which are defined by only one delay-differential equation are attractive due to their simple model. On the other hand, it is possible to synchronize to the future states of a time-delay chaotic system by anticipating synchronization. Therefore, random number generator (RNG), which employs such a system, might not be immune to the attacks. In this paper, attack on a chaos-based random number generator using anticipating synchronization is investigated. The considered time-delay chaotic system produces binary signals, which can directly be used as a source of RNG. Anticipating synchronization is obtained by incorporating other systems appropriately coupled to the original one. Quantification of synchronization is given by the bit error between the streams produced by the original and coupled systems. It is shown that the bit streams generated by the original system can be anticipated by the coupled systems beforehand.}},
doi = {https://doi.org/10.1142/S0218127415500212}}
[J2]
Yalçın, M.E., Yeniçeri, R., Özoğuz, S.,
"A chaotic Time-delay Sampled-data System and Its Implementation,"
International Journal of Bifurcation and Chaos, vol.24, no.3, 2014.
@article{yenicerirJ2,
author = {Yalcin, Mustak Erhan and Yeniceri, Ramazan and Ozoguz, Serdar},
title = {A Chaotic Time-Delay Sampled-Data System and Its Implementation},
journal = {{International Journal of Bifurcation and Chaos}},
volume = {24},
number = {03},
pages = {1450039},
year = {2014},
keywords = {sampled-data system, circuit implementation, time-delay system, delay differential equations},
abstract = {{Chaotic time-delay systems are attractive candidates to generate chaotic dynamics because of their relatively simple system model. The circuit realization of the time-delay part is the main drawback of these systems. In order to overcome this drawback, a chaotic time-delay system which features a binary feedback function is presented. The use of binary feedback function results in a considerably simplified implementation of the time-delay unit based on using a flip-flop chain. Modeling the system thus obtained yields a chaotic sampled-data system. The existence of chaotic dynamics in the introduced sampled-data systems is numerically verified by calculating system Lyapunov exponents and applying a detailed bifurcation analysis. The chaotic attractor of the introduced sampled-data system is verified by the circuit realization of the system. In order to minimize the number of flip-flops in the chain while keeping the system in chaos, the spectrum of Lyapunov exponent versus clock frequency of the flip-flops and a bifurcation parameter is computed. The circuit realization of the introduced sampled-data system includes a relatively simple structure compared to other chaotic time-delay systems and this overcomes the complexity of the circuit implementation of the time-delay block.}},
doi = {https://doi.org/10.1142/S0218127414500394}}
author = {Yalcin, Mustak Erhan and Yeniceri, Ramazan and Ozoguz, Serdar},
title = {A Chaotic Time-Delay Sampled-Data System and Its Implementation},
journal = {{International Journal of Bifurcation and Chaos}},
volume = {24},
number = {03},
pages = {1450039},
year = {2014},
keywords = {sampled-data system, circuit implementation, time-delay system, delay differential equations},
abstract = {{Chaotic time-delay systems are attractive candidates to generate chaotic dynamics because of their relatively simple system model. The circuit realization of the time-delay part is the main drawback of these systems. In order to overcome this drawback, a chaotic time-delay system which features a binary feedback function is presented. The use of binary feedback function results in a considerably simplified implementation of the time-delay unit based on using a flip-flop chain. Modeling the system thus obtained yields a chaotic sampled-data system. The existence of chaotic dynamics in the introduced sampled-data systems is numerically verified by calculating system Lyapunov exponents and applying a detailed bifurcation analysis. The chaotic attractor of the introduced sampled-data system is verified by the circuit realization of the system. In order to minimize the number of flip-flops in the chain while keeping the system in chaos, the spectrum of Lyapunov exponent versus clock frequency of the flip-flops and a bifurcation parameter is computed. The circuit realization of the introduced sampled-data system includes a relatively simple structure compared to other chaotic time-delay systems and this overcomes the complexity of the circuit implementation of the time-delay block.}},
doi = {https://doi.org/10.1142/S0218127414500394}}
[J1]
Yeniçeri, R., Yalçın, M.E.,
"True Random Bit Generation with Time-delay Sampled-data Feedback System,"
Electronics Letters, vol.49, no.8, pp.543-545, April 11, 2013.
@article{yenicerirJ1,
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {True random bit generation with time-delay sampled-data feedback system},
journal = {{Electronics Letters}},
volume = {49},
number = {8},
pages = {543-545},
year = {2013},
abstract = {{A new true random bit generator circuit which is a time-delay sampled-data feedback system is proposed. The differential equation that defines the dynamic behaviour of the circuit is implemented by analogue active and passive components with a digital block that forms the sample and hold delay line as the feedback. A D-type flip-flop chain is used on the delayed feedback line due to the feedback signal which is a binary signal. The impressive features of the circuit are the ease of its implementation and the successful statistical analysis results that show its output is random. Furthermore, the reported system is the first true random bit generator using a time-delay sampled-data feedback system.}},
keywords = {{differential equations, feedback, flip-flops, random number generation, sample and hold circuits, sampled data circuits, statistical analysis, time-delay sampled-data feedback system, true random bit generator circuit, differential equation, dynamic behaviour, analogue component, active component, passive component, digital block, sample-and-hold delay line, D-type flip-flop chain, feedback signal, binary signal, statistical analysis, differential equations, feedback, flip-flops, random number generation, sample and hold circuits, sampled data circuits, statistical analysis, time-delay sampled-data feedback system, true random bit generator circuit, differential equation, dynamic behaviour, analogue component, active component, passive component, digital block, sample-and-hold delay line, D-type flip-flop chain, feedback signal, binary signal, statistical analysis}},
doi = {https://doi.org/10.1049/el.2012.3448}}
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {True random bit generation with time-delay sampled-data feedback system},
journal = {{Electronics Letters}},
volume = {49},
number = {8},
pages = {543-545},
year = {2013},
abstract = {{A new true random bit generator circuit which is a time-delay sampled-data feedback system is proposed. The differential equation that defines the dynamic behaviour of the circuit is implemented by analogue active and passive components with a digital block that forms the sample and hold delay line as the feedback. A D-type flip-flop chain is used on the delayed feedback line due to the feedback signal which is a binary signal. The impressive features of the circuit are the ease of its implementation and the successful statistical analysis results that show its output is random. Furthermore, the reported system is the first true random bit generator using a time-delay sampled-data feedback system.}},
keywords = {{differential equations, feedback, flip-flops, random number generation, sample and hold circuits, sampled data circuits, statistical analysis, time-delay sampled-data feedback system, true random bit generator circuit, differential equation, dynamic behaviour, analogue component, active component, passive component, digital block, sample-and-hold delay line, D-type flip-flop chain, feedback signal, binary signal, statistical analysis, differential equations, feedback, flip-flops, random number generation, sample and hold circuits, sampled data circuits, statistical analysis, time-delay sampled-data feedback system, true random bit generator circuit, differential equation, dynamic behaviour, analogue component, active component, passive component, digital block, sample-and-hold delay line, D-type flip-flop chain, feedback signal, binary signal, statistical analysis}},
doi = {https://doi.org/10.1049/el.2012.3448}}
Conference Papers
[M40]
Cengiz, S.K., Abu-Khalaf, M., Yeniçeri, R.,
"A Review of Multidimensional Assignment in Multi-Sensor Multi-Target Tracking,"
24th Integrated Communications, Navigation, and Surveillance Conference (ICNS),
Westin Washington Dulles Airport, Herndon, Virginia, USA, April 23-25, 2024.
[M39]
Yiğit, E.E., Yeniçeri, R.,
"FPGA Based Hardware Accelerator for Euler Equations with Finite Volume Method,"
AIAA SCITECH 2024 Forum,
Orlando, Florida, January 8-12, 2024.
@inproceedings{yenicerirM39,
author = {Emine Elif Yiğit and Ramazan Yeniçeri},
title = {{FPGA Based Hardware Accelerator for Euler Equations with Finite Volume Method}},
booktitle = {{AIAA SCITECH 2024 Forum}},
year = {2024},
month = {Jan},
pages = {1-24},
abstract = {{Computational Fluid Dynamic (CFD) is of great importance in the design and analysis of aircraft. The utilization of CFD enables the improvement of aircraft design, cost reduction, enhanced energy efficiency, and optimization of aircraft performance. By conducting realistic CFD simulations prior to production, the performance of the designed aircraft can be thoroughly tested. CFD solves complex equations numerically to analyze fluid flow, hence requiring substantial computational power and time. Presently, high-core-count computers are available to facilitate these calculations. However, the cost of such computers is considerably high. Therefore, we propose the development of an Field Programmable Gate Array (FPGA) based CFD accelerator to reduce computation time and cost. The focus is on designing an FPGA based Euler Equations solver for high-speed flow simulations. The two-dimensional Euler Equations are derived and discretized using the Finite Volume Method (FVM). MATLAB scripts are developed for the solver, resulting in the generation of core script files that created intial model. A MATLAB simulator is developed using these files. The simulator’s performance is validated against ANSYS Fluent analysis. Once validated, the initial model are transferred to the MATLAB HDLcoder environment. In HDLcoder, hardware design is performed for a single finite volume, utilizing information from the simulation logger stored in the idea step. The model undergoes elaboration and high-level synthesis. The resulting HDLcoder model generates synthesizable HDL (Hardware Description Language) code for FPGA implementation. Verification and evaluation are conducted using the simulation logger results. FPGA resource utilization was analyzed and the speed of the accelerator was compared with the Central Process Unit (CPU).}},
doi = {10.2514/6.2024-0044}}
author = {Emine Elif Yiğit and Ramazan Yeniçeri},
title = {{FPGA Based Hardware Accelerator for Euler Equations with Finite Volume Method}},
booktitle = {{AIAA SCITECH 2024 Forum}},
year = {2024},
month = {Jan},
pages = {1-24},
abstract = {{Computational Fluid Dynamic (CFD) is of great importance in the design and analysis of aircraft. The utilization of CFD enables the improvement of aircraft design, cost reduction, enhanced energy efficiency, and optimization of aircraft performance. By conducting realistic CFD simulations prior to production, the performance of the designed aircraft can be thoroughly tested. CFD solves complex equations numerically to analyze fluid flow, hence requiring substantial computational power and time. Presently, high-core-count computers are available to facilitate these calculations. However, the cost of such computers is considerably high. Therefore, we propose the development of an Field Programmable Gate Array (FPGA) based CFD accelerator to reduce computation time and cost. The focus is on designing an FPGA based Euler Equations solver for high-speed flow simulations. The two-dimensional Euler Equations are derived and discretized using the Finite Volume Method (FVM). MATLAB scripts are developed for the solver, resulting in the generation of core script files that created intial model. A MATLAB simulator is developed using these files. The simulator’s performance is validated against ANSYS Fluent analysis. Once validated, the initial model are transferred to the MATLAB HDLcoder environment. In HDLcoder, hardware design is performed for a single finite volume, utilizing information from the simulation logger stored in the idea step. The model undergoes elaboration and high-level synthesis. The resulting HDLcoder model generates synthesizable HDL (Hardware Description Language) code for FPGA implementation. Verification and evaluation are conducted using the simulation logger results. FPGA resource utilization was analyzed and the speed of the accelerator was compared with the Central Process Unit (CPU).}},
doi = {10.2514/6.2024-0044}}
[M38]
Şenel, S., Yeniçeri, R.,
"A Hardware Accelerator Design for Quaternion to Euler Angles,"
IEEE 30th International Conference on Electronics, Circuits and Systems (ICECS),
Istanbul, Türkiye, December 4-7, 2023.
@inproceedings{yenicerirM38,
author = {Şenel, Serkan and Yençeri, Ramazan},
title = {{A Hardware Accelerator Design for Quaternion to Euler Angles Conversion}},
booktitle = {{2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)}},
year = {2023},
month = {Dec},
pages = {1-4},
abstract = {{This paper describes a hardware accelerator design for converting quaternion to Euler angles using High Level Synthesis methodology. As a design methodology, automatic code generation from Simulink model, prototyping device, number representation, formulation, basic operators and basic functions are explained. A successful implementation is presented by giving validation and synthesis results.}},
keywords = {{High-level synthesis, HLS, quaternion, Euler angles, HDL code generation}},
doi = {10.1109/ICECS58634.2023.10382806}}
author = {Şenel, Serkan and Yençeri, Ramazan},
title = {{A Hardware Accelerator Design for Quaternion to Euler Angles Conversion}},
booktitle = {{2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)}},
year = {2023},
month = {Dec},
pages = {1-4},
abstract = {{This paper describes a hardware accelerator design for converting quaternion to Euler angles using High Level Synthesis methodology. As a design methodology, automatic code generation from Simulink model, prototyping device, number representation, formulation, basic operators and basic functions are explained. A successful implementation is presented by giving validation and synthesis results.}},
keywords = {{High-level synthesis, HLS, quaternion, Euler angles, HDL code generation}},
doi = {10.1109/ICECS58634.2023.10382806}}
[M37]
Hüner, Y., Yeniçeri, R.,
"ComCoS: Enhanced Cache Partitioning Technique for Integrated Modular Avionics,"
26th Euromicro Conference on Digital System Design (DSD'2023),
Durres, Albania, September 6-8, 2023.
@inproceedings{yenicerirM37,
author = {Huner, Yakup and Yeniceri, Ramazan},
title = {{ComCoS: Enhanced Cache Partitioning Technique for Integrated Modular Avionics}},
booktitle = {{26th Euromicro Conference on Digital System Design (DSD'2023)}},
year = {2023},
month = {September},
pages = {},
abstract = {{Integrated Modular Avionics (IMA) has been widely used in safety-critical aviation applications over the last 20 years due to its reusability, portability, modularity, and cost-effective re-certification. IMA-based systems effectively manage numerous applications with varying levels of criticality by utilizing shared hardware and middleware supported by hardware-independent APIs like the ARINC 653 standard. Although the ARINC 653 standard provides robust time and memory partitioning, there are significant determinism problems due to shared cache usage in multicore platforms. This issue can be resolved by cache partitioning, allowing applications to run in separate memory regions. This paper proposes a novel cache partitioning technique, called ComCoS, for operating systems with better performance and determinism while preserving safety. In our experiments on an ARINC 653 compatible real-time operating system, our technique provides an average 52% faster performance and 2.91 times lower standard deviation in memory distribution. The ComCoS technique improves 3.48 times in Worst-Case Execution Time (WCET) and reduces the standard deviation by a factor of 6.23 in the memory allocation service.}},
keywords = {{Integrated Modular Avionics, Cache Partitioning, Memory Management, WCET, ARINC 653, DO-178C}},
doi = {}}
author = {Huner, Yakup and Yeniceri, Ramazan},
title = {{ComCoS: Enhanced Cache Partitioning Technique for Integrated Modular Avionics}},
booktitle = {{26th Euromicro Conference on Digital System Design (DSD'2023)}},
year = {2023},
month = {September},
pages = {},
abstract = {{Integrated Modular Avionics (IMA) has been widely used in safety-critical aviation applications over the last 20 years due to its reusability, portability, modularity, and cost-effective re-certification. IMA-based systems effectively manage numerous applications with varying levels of criticality by utilizing shared hardware and middleware supported by hardware-independent APIs like the ARINC 653 standard. Although the ARINC 653 standard provides robust time and memory partitioning, there are significant determinism problems due to shared cache usage in multicore platforms. This issue can be resolved by cache partitioning, allowing applications to run in separate memory regions. This paper proposes a novel cache partitioning technique, called ComCoS, for operating systems with better performance and determinism while preserving safety. In our experiments on an ARINC 653 compatible real-time operating system, our technique provides an average 52% faster performance and 2.91 times lower standard deviation in memory distribution. The ComCoS technique improves 3.48 times in Worst-Case Execution Time (WCET) and reduces the standard deviation by a factor of 6.23 in the memory allocation service.}},
keywords = {{Integrated Modular Avionics, Cache Partitioning, Memory Management, WCET, ARINC 653, DO-178C}},
doi = {}}
[M36]
Gayretli, M.G., Yeniçeri, R., Demir, M.S., Hökelek, İ.,
"Work-in-Progress: An OMNET++ Simulation Model for IMA Systems,"
IEEE International Black Sea Conference on Communications and Networking (BlackSeaCom 2023),
Istanbul, Türkiye, July 4-7, 2023.
@inproceedings{yenicerirM36,
author = {Gayretli, Mumin Gayretli and Yeniceri, Ramazan and Demir, M. Selim and Hokelek, Ibrahim},
title = {{Work-in-Progress: An OMNET++ Simulation Model for IMA Systems}},
booktitle = {{IEEE International Black Sea Conference on Communications and Networking (BlackSeaCom 2023)}},
year = {2023},
month = {July},
pages = {},
abstract = {{Integrated Modular Avionics (IMA) architecture is designed to integrate units with different applications on a single hardware platform. It has many configuration parameters and design options that affect system and network performance, so estimating the system's behavior can only be accessible if the complete system is executed. Therefore, implementing an avionic system in a simulation environment simplifies finding the optimum system settings. Moreover, this enables engineers to build system prototypes without performing any physical effort. The contribution of this paper is to develop a simulation model of an IMA system in the OMNET++ simulator, to evaluate the network performance of IMA systems. The proposed model is validated using an example scenario with application delay and packet loss ratio metrics.}},
doi = {10.1109/BlackSeaCom58138.2023.10299693}}
author = {Gayretli, Mumin Gayretli and Yeniceri, Ramazan and Demir, M. Selim and Hokelek, Ibrahim},
title = {{Work-in-Progress: An OMNET++ Simulation Model for IMA Systems}},
booktitle = {{IEEE International Black Sea Conference on Communications and Networking (BlackSeaCom 2023)}},
year = {2023},
month = {July},
pages = {},
abstract = {{Integrated Modular Avionics (IMA) architecture is designed to integrate units with different applications on a single hardware platform. It has many configuration parameters and design options that affect system and network performance, so estimating the system's behavior can only be accessible if the complete system is executed. Therefore, implementing an avionic system in a simulation environment simplifies finding the optimum system settings. Moreover, this enables engineers to build system prototypes without performing any physical effort. The contribution of this paper is to develop a simulation model of an IMA system in the OMNET++ simulator, to evaluate the network performance of IMA systems. The proposed model is validated using an example scenario with application delay and packet loss ratio metrics.}},
doi = {10.1109/BlackSeaCom58138.2023.10299693}}
[M35]
Yeniçeri, R., Koyuncu, E., Şenel, S., Paşaoğlu, M.Z., Çetin, A.T., Ösken, İ., Sevimli, O., Çetin, G., Yalçın, B., İrez, M., İnal, T.T., Toksöz, M.A.,
"A Multi-drone System for Formation Flight and Solo Attack,"
10th International Conference on Recent Advances in Air and Space Technologies (RAST 2023),
Istanbul, Türkiye, June 7-9, 2023.
@inproceedings{yenicerirM35,
author = {Yeniceri, Ramazan and Koyuncu, Emre and Senel, Serkan and Pasaoglu, Mehmet Zeki and Cetin, Ahmet Talha and Osken, Ipek and Sevimli, Onur and Cetin, Gurkan and Yalcin, Baris and Irez, Mert and Inal, Taha Taner and Toksoz, Mehmet Altan},
title = {{A Multi-drone System for Formation Flight and Solo Attack}},
booktitle = {{2023 10th International Conference on Recent Advances in Air and Space Technologies (RAST)}},
year = {2023},
month = {June},
pages = {1-6},
abstract = {{In this paper, the dynamic model and model validation of agile micro drones, capable of formation flight and solo attack, are presented. The hardware architecture of drones, their features, ground systems required for operation are introduced. Developed software modules, and their formation flight route plan and attack route plan generation features are explained. The results from real-flight tests are covered.}},
keywords = {{UAV}, multi-drone, swarm, formation flight},
doi = {https://doi.org/10.1109/RAST57548.2023.10198012}}
author = {Yeniceri, Ramazan and Koyuncu, Emre and Senel, Serkan and Pasaoglu, Mehmet Zeki and Cetin, Ahmet Talha and Osken, Ipek and Sevimli, Onur and Cetin, Gurkan and Yalcin, Baris and Irez, Mert and Inal, Taha Taner and Toksoz, Mehmet Altan},
title = {{A Multi-drone System for Formation Flight and Solo Attack}},
booktitle = {{2023 10th International Conference on Recent Advances in Air and Space Technologies (RAST)}},
year = {2023},
month = {June},
pages = {1-6},
abstract = {{In this paper, the dynamic model and model validation of agile micro drones, capable of formation flight and solo attack, are presented. The hardware architecture of drones, their features, ground systems required for operation are introduced. Developed software modules, and their formation flight route plan and attack route plan generation features are explained. The results from real-flight tests are covered.}},
keywords = {{UAV}, multi-drone, swarm, formation flight},
doi = {https://doi.org/10.1109/RAST57548.2023.10198012}}
[M34]
Büyükçolak, Ö.S., Yeniçeri, R.,
"Quadrotor Model Implementation on Raspberry Pi Zero and Pi 4 Boards using FreeRTOS,"
12th Mediterranean Conference on Embedded Computing (MECO),
Budva, Montenegro, June 6-10, 2023.
@inproceedings{yenicerirM34,
author = {Buyukcolak, Omer Serhat and Yeniceri, Ramazan},
title = {{Quadrotor Model Implementation on Raspberry Pi Zero and Pi 4 Boards using FreeRTOS}},
booktitle = {{2023 12th Mediterranean Conference on Embedded Computing (MECO)}},
year = {2023},
month = {June},
pages = {1-4},
abstract = {{In this study, a 6 degrees of freedom(DOF) quadrotor flight simulation scenario is implemented on Raspberry Pi zero and Pi 4 boards, using FreeRTOS. Main aim for this work is to define an intermediate environment, much like a test bench, so that, realizing with the real hardware is as smooth as possible. Keeping this in mind, Raspberry boards are used with FreeRTOS operating system. Quadrotor model is implemented on Pi zero as a high priority task, and similarly, controller is implemented on Pi 4 board. FreeRTOS is not officially supported for raspberry boards, therefore, operating system is ported for both boards. Communication between boards is handled using on board UART devices. Performance analysis and practicality of the proposed system is discussed.}},
keywords = {quadrotor, real-time, simulation, {UART}, {Raspberry Pi}, {FreeRTOS}},
doi = {https://doi.org/10.1109/MECO58584.2023.10154999}}
author = {Buyukcolak, Omer Serhat and Yeniceri, Ramazan},
title = {{Quadrotor Model Implementation on Raspberry Pi Zero and Pi 4 Boards using FreeRTOS}},
booktitle = {{2023 12th Mediterranean Conference on Embedded Computing (MECO)}},
year = {2023},
month = {June},
pages = {1-4},
abstract = {{In this study, a 6 degrees of freedom(DOF) quadrotor flight simulation scenario is implemented on Raspberry Pi zero and Pi 4 boards, using FreeRTOS. Main aim for this work is to define an intermediate environment, much like a test bench, so that, realizing with the real hardware is as smooth as possible. Keeping this in mind, Raspberry boards are used with FreeRTOS operating system. Quadrotor model is implemented on Pi zero as a high priority task, and similarly, controller is implemented on Pi 4 board. FreeRTOS is not officially supported for raspberry boards, therefore, operating system is ported for both boards. Communication between boards is handled using on board UART devices. Performance analysis and practicality of the proposed system is discussed.}},
keywords = {quadrotor, real-time, simulation, {UART}, {Raspberry Pi}, {FreeRTOS}},
doi = {https://doi.org/10.1109/MECO58584.2023.10154999}}
[M33]
Yeniçeri, R., Koyuncu, E., Ösken, İ., Cásek, P., Pálenská, M., Orhan, İ., Yapıcıoğlu, H., Açıkel, B., Turhan, U., Diken, M.O., Sternemann, K., Pouzet, J., Doetsch, U.,
"Towards Full Integration of Manned and Unmanned Air Traffic: A Test Case Study - Performance Results of Future All Aviation CNS Technology (FACT) Project,"
23rd Integrated Communications, Navigation, and Surveillance Conference (ICNS),
Westin Washington Dulles Airport, Herndon, Virginia, USA, April 18-20, 2023.
@inproceedings{yenicerirM33,
author = {Yeniceri, Ramazan and Koyuncu, Emre and Osken, Ipek and Casek, Petr and Palenska, Marketa and Orhan, Ilkay and Yapicioglu, Haluk and Acikel, Birsen and Turhan, Ugur and Diken, Mustafa Oguz and Sternemann, Klaus-Peter and Pouzet, Jacky and Doetsch, Uwe},
title = {{Towards Full Integration of Manned and Unmanned Air Traffic: A Test Case Study – Performance Results of Future All Aviation CNS Technology (FACT) Project}},
booktitle = {{2023 Integrated Communication, Navigation and Surveillance Conference (ICNS)}},
year = {2023},
month = {April},
pages = {1-8},
abstract = {{This paper presents results of real flight evaluation of integrated communication, navigation and surveillance solution equipment for both manned and unmanned aerial vehicles aiming to share the same airspace. An equipment set, consisting of an experimental CNS device connected to Internet over an LTE modem with a proper antenna, and own battery is developed and installed on an aircraft, a rotorcraft and two drones. The usability of this equipment is evaluated from both technical and operational point of view in the UTM and ATM reflexes exhibited in the cases of area violation and route deviation of manned / unmanned aerial vehicles in controlled and uncontrolled airspace.}},
keywords = {{CNS}, airspace, integration, {ATM}, {UTM}},
doi = {https://doi.org/10.1109/ICNS58246.2023.10124293}}
author = {Yeniceri, Ramazan and Koyuncu, Emre and Osken, Ipek and Casek, Petr and Palenska, Marketa and Orhan, Ilkay and Yapicioglu, Haluk and Acikel, Birsen and Turhan, Ugur and Diken, Mustafa Oguz and Sternemann, Klaus-Peter and Pouzet, Jacky and Doetsch, Uwe},
title = {{Towards Full Integration of Manned and Unmanned Air Traffic: A Test Case Study – Performance Results of Future All Aviation CNS Technology (FACT) Project}},
booktitle = {{2023 Integrated Communication, Navigation and Surveillance Conference (ICNS)}},
year = {2023},
month = {April},
pages = {1-8},
abstract = {{This paper presents results of real flight evaluation of integrated communication, navigation and surveillance solution equipment for both manned and unmanned aerial vehicles aiming to share the same airspace. An equipment set, consisting of an experimental CNS device connected to Internet over an LTE modem with a proper antenna, and own battery is developed and installed on an aircraft, a rotorcraft and two drones. The usability of this equipment is evaluated from both technical and operational point of view in the UTM and ATM reflexes exhibited in the cases of area violation and route deviation of manned / unmanned aerial vehicles in controlled and uncontrolled airspace.}},
keywords = {{CNS}, airspace, integration, {ATM}, {UTM}},
doi = {https://doi.org/10.1109/ICNS58246.2023.10124293}}
[M32]
Memiş, S., Yeniçeri, R.,
"Towards FPGA Based Digital Twin of UAV Swarms: An Area Efficient Hardware Accelerator of Transformation Matrix of 6-DoF Block,"
AIAA SCITECH 2023 Forum,
National Harbor, MD, January 23-27, 2023.
@inproceedings{yenicerirM32,
author = {Memis, Sezer and Yeniceri, Ramazan},
title = {{Towards FPGA Based Digital Twin of UAV Swarms: An Area Efficient Hardware Accelerator of Transformation Matrix of 6-DoF Block}},
booktitle = {{AIAA SCITECH 2023 Forum}},
year = {2023},
month = {January},
pages = {2130-2144},
abstract = {{View Video Presentation: https://doi.org/10.2514/6.2023-2130.vidModeling the dynamic behavior of quadrotors with high accuracy is of great importance for controller and estimator design and realistic simulations of the whole system. A problem encountered here is in software-based simulations, which are generally used, when the accuracy of the system model increases, the simulation speed decreases considerably. In other words, there is a trade-off between simulation speed and system dynamics accuracy. To enhance this trade-off, system dynamics can be implemented based on hardware using FPGAs. Hardware-based simulation capability provides high speed and high accuracy. In this paper, transformation matrices in the 6-DoF mathematical model used to calculate the positions and orientations of quadrotors are targeted for hardware-based implementation. In simulations, it is aimed to design a hardware block that calculates the transformation matrix for the given Euler angles in a shorter time according to the software-based implementation. In this design, Taylor series expansion with the quarter-wave symmetry and Newton-Raphson division algorithm methods are chosen as the trigonometric function approximation. The fixed-point number representation method is chosen for FPGA implementation. After determining the dynamic range of the design, fixed-point word and fraction lengths are determined according to the DSP blocks and quarter-wave symmetry requirements on the FPGAs. Then, the system is designed using a Simulink environment, which consists of a datapath that uses the limited hardware resources on the FPGA and a state machine that controls this datapath. While designing the datapath as less as possible multipliers/adders are used. Finally, the system, whose accuracy is tested in the Simulink environment, is synthesized in Verilog language with automatic code generation method. In this article, a transformation matrix calculator needed in 6-DoF equations is designed using a hardware-based controller/datapath implementation that runs faster than a software-based implementation and consumes less resource on the FPGA.}},
doi = {https://doi.org/10.2514/6.2023-2130}}
author = {Memis, Sezer and Yeniceri, Ramazan},
title = {{Towards FPGA Based Digital Twin of UAV Swarms: An Area Efficient Hardware Accelerator of Transformation Matrix of 6-DoF Block}},
booktitle = {{AIAA SCITECH 2023 Forum}},
year = {2023},
month = {January},
pages = {2130-2144},
abstract = {{View Video Presentation: https://doi.org/10.2514/6.2023-2130.vidModeling the dynamic behavior of quadrotors with high accuracy is of great importance for controller and estimator design and realistic simulations of the whole system. A problem encountered here is in software-based simulations, which are generally used, when the accuracy of the system model increases, the simulation speed decreases considerably. In other words, there is a trade-off between simulation speed and system dynamics accuracy. To enhance this trade-off, system dynamics can be implemented based on hardware using FPGAs. Hardware-based simulation capability provides high speed and high accuracy. In this paper, transformation matrices in the 6-DoF mathematical model used to calculate the positions and orientations of quadrotors are targeted for hardware-based implementation. In simulations, it is aimed to design a hardware block that calculates the transformation matrix for the given Euler angles in a shorter time according to the software-based implementation. In this design, Taylor series expansion with the quarter-wave symmetry and Newton-Raphson division algorithm methods are chosen as the trigonometric function approximation. The fixed-point number representation method is chosen for FPGA implementation. After determining the dynamic range of the design, fixed-point word and fraction lengths are determined according to the DSP blocks and quarter-wave symmetry requirements on the FPGAs. Then, the system is designed using a Simulink environment, which consists of a datapath that uses the limited hardware resources on the FPGA and a state machine that controls this datapath. While designing the datapath as less as possible multipliers/adders are used. Finally, the system, whose accuracy is tested in the Simulink environment, is synthesized in Verilog language with automatic code generation method. In this article, a transformation matrix calculator needed in 6-DoF equations is designed using a hardware-based controller/datapath implementation that runs faster than a software-based implementation and consumes less resource on the FPGA.}},
doi = {https://doi.org/10.2514/6.2023-2130}}
[M31]
Cengiz, S.K., Sarı, A.A., Çerkezoğlu, A., Yılmaz, M.H., Yeniçeri, R.,
"ARCHI-Pilot: A Model-Based Autopilot Software Implementation using FreeRTOS with Automatic Code Generation,"
AIAA SCITECH 2023 Forum,
National Harbor, MD, January 23-27, 2023.
@inproceedings{yenicerirM31,
author = {Cengiz, Said Kemal and Sari, Ayse Aysu and Cerkezoglu, Abdullah and Yilmaz, Muhammed Huseyin and Yeniceri, Ramazan},
title = {{ARCHI-Pilot: A Model-Based Autopilot Software Implementation using FreeRTOS with Automatic Code Generation}},
booktitle = {{AIAA SCITECH 2023 Forum}},
year = {2023},
month = {January},
pages = {1125-1142},
abstract = {{View Video Presentation: https://doi.org/10.2514/6.2023-1125.vidModularity, portability, and flexibility have become a trend with increasing momentum gradually, in the software community. ARCHI-Pilot is an autopilot software designed to catch the aforementioned trend. ARCHI-Pilot software, designed in a modular structure to work with open-source FreeRTOS and solve the problem of inter-module communication with its Data Distribution Service. Model is designed in MATLAB/Simulink environment including the basic parts of an autopilot software such as: navigation, control and guidance, then implemented by combining the pieces of code, which are obtained by code generation, with in FreeRTOS and Data Distribution Service. Therefore, the architecture can continue to be developed rapidly in the simulation environment and released easily.}},
doi = {https://doi.org/10.2514/6.2023-1125}}
author = {Cengiz, Said Kemal and Sari, Ayse Aysu and Cerkezoglu, Abdullah and Yilmaz, Muhammed Huseyin and Yeniceri, Ramazan},
title = {{ARCHI-Pilot: A Model-Based Autopilot Software Implementation using FreeRTOS with Automatic Code Generation}},
booktitle = {{AIAA SCITECH 2023 Forum}},
year = {2023},
month = {January},
pages = {1125-1142},
abstract = {{View Video Presentation: https://doi.org/10.2514/6.2023-1125.vidModularity, portability, and flexibility have become a trend with increasing momentum gradually, in the software community. ARCHI-Pilot is an autopilot software designed to catch the aforementioned trend. ARCHI-Pilot software, designed in a modular structure to work with open-source FreeRTOS and solve the problem of inter-module communication with its Data Distribution Service. Model is designed in MATLAB/Simulink environment including the basic parts of an autopilot software such as: navigation, control and guidance, then implemented by combining the pieces of code, which are obtained by code generation, with in FreeRTOS and Data Distribution Service. Therefore, the architecture can continue to be developed rapidly in the simulation environment and released easily.}},
doi = {https://doi.org/10.2514/6.2023-1125}}
[M30]
Işkın, M.E., Sevgili, S.O., Yeniçeri, R.,
"Auto Relay Handover Method for Extended Star Topology UAV Networks,"
12th International Conference on Mechanical and Aerospace Engineering (ICMAE2021),
Athens, Greece, July 16-19, 2021.
@inproceedings{yenicerirM30,
author = {Iskin, Mustafa Ensar and Sevgili, Seyyid Osman and Yeniceri, Ramazan},
title = {{Auto Relay Handover Method for Extended Star Topology UAV Networks}},
booktitle = {{2021 12th International Conference on Mechanical and Aerospace Engineering (ICMAE)}},
year = {2021},
month = {July},
pages = {378-383},
abstract = {{This paper presents the development of a new autonomous relay handover method based on a widely used open-source and low-cost UAV telemetry radio. Instead of ad-hoc topology, extended star topology is preferred due to its simplicity. The default statistical time division multiplexing mechanism of the selected radio is explained. Four improvements over the default features and the obtained benefits for UAV communication are described. Verification of the proposed method is conducted with a ground test and the results are presented.}},
keywords = {telemetry, time division multiplexing, unmanned aerial vehicle, star topology, ad-hoc network},
doi = {https://doi.org/10.1109/ICMAE52228.2021.9522498}}
author = {Iskin, Mustafa Ensar and Sevgili, Seyyid Osman and Yeniceri, Ramazan},
title = {{Auto Relay Handover Method for Extended Star Topology UAV Networks}},
booktitle = {{2021 12th International Conference on Mechanical and Aerospace Engineering (ICMAE)}},
year = {2021},
month = {July},
pages = {378-383},
abstract = {{This paper presents the development of a new autonomous relay handover method based on a widely used open-source and low-cost UAV telemetry radio. Instead of ad-hoc topology, extended star topology is preferred due to its simplicity. The default statistical time division multiplexing mechanism of the selected radio is explained. Four improvements over the default features and the obtained benefits for UAV communication are described. Verification of the proposed method is conducted with a ground test and the results are presented.}},
keywords = {telemetry, time division multiplexing, unmanned aerial vehicle, star topology, ad-hoc network},
doi = {https://doi.org/10.1109/ICMAE52228.2021.9522498}}
[M29]
Yeniçeri, R., Saldıran, E.,
"Design and Development of An Avionics Architecture for Autonomous UAV Fleets,"
12th International Conference on Mechanical and Aerospace Engineering (ICMAE2021),
Athens, Greece, July 16-19, 2021.
@inproceedings{yenicerirM29,
author = {Yeniceri, Ramazan and Saldiran, Emre},
title = {{Design and Development of An Avionics Architecture for Autonomous UAV Fleets}},
booktitle = {{2021 12th International Conference on Mechanical and Aerospace Engineering (ICMAE)}},
year = {2021},
month = {July},
pages = {365-372},
abstract = {{In this work we present the design and development process of an avionics architecture for missions that require highly coordinated flight of a fleet of autonomous fixed-wing micro UAVs. Applications such as signal tracking or dynamic object tracking with multiple UAVs allow a cost-effective and minimum-risk alternative to missions which have been historically handled with manned aircraft. As such, for these specific applications, we have developed a micro-avionics architecture structured around an in-house customized open-source autopilot and an indigenous Linux based single board payload/flight management computer. The essential 5-km range telemetry and control link radio is backed up by high-power long-range IEEE 802.11n (WiFi) radio device. The redundancy of communication not only improves the reliability of the avionics architecture, but also enables the trade-off between bandwidth and power efficiency. The architecture is capable of transmitting data at rates above 200 kbps up to 4 km away from its ground station equipped with the developed miniature patch antenna tracker. The payload/flight management computer is ready to run a CSI/USB connected day-light or low-illumination infra-red camera, a USB connected software defined radio and different types of sensor payloads such as radar/lidar range sensors and RGBD cameras. Tied to this architecture, we have designed a Software-in-the-Loop (SIL) and Hardware-in-the-Loop (HIL) testing system with MAVlink communication protocol interlinking hardware to Matlab based UAV dynamic models and tracking algorithms. This system allows comprehensive simulation and testing of designed control and guidance algorithms before flight tests while minimizing cost and crash risk. We have successfully used the avionics architecture in flight tests that involve (a) system identification of flight vehicles and (b) tracking and identification of signal sources using multiple UAVs.}},
keywords = {unmanned aerial vehicles, avionics, swarm},
doi = {https://doi.org/10.1109/ICMAE52228.2021.9522365}}
author = {Yeniceri, Ramazan and Saldiran, Emre},
title = {{Design and Development of An Avionics Architecture for Autonomous UAV Fleets}},
booktitle = {{2021 12th International Conference on Mechanical and Aerospace Engineering (ICMAE)}},
year = {2021},
month = {July},
pages = {365-372},
abstract = {{In this work we present the design and development process of an avionics architecture for missions that require highly coordinated flight of a fleet of autonomous fixed-wing micro UAVs. Applications such as signal tracking or dynamic object tracking with multiple UAVs allow a cost-effective and minimum-risk alternative to missions which have been historically handled with manned aircraft. As such, for these specific applications, we have developed a micro-avionics architecture structured around an in-house customized open-source autopilot and an indigenous Linux based single board payload/flight management computer. The essential 5-km range telemetry and control link radio is backed up by high-power long-range IEEE 802.11n (WiFi) radio device. The redundancy of communication not only improves the reliability of the avionics architecture, but also enables the trade-off between bandwidth and power efficiency. The architecture is capable of transmitting data at rates above 200 kbps up to 4 km away from its ground station equipped with the developed miniature patch antenna tracker. The payload/flight management computer is ready to run a CSI/USB connected day-light or low-illumination infra-red camera, a USB connected software defined radio and different types of sensor payloads such as radar/lidar range sensors and RGBD cameras. Tied to this architecture, we have designed a Software-in-the-Loop (SIL) and Hardware-in-the-Loop (HIL) testing system with MAVlink communication protocol interlinking hardware to Matlab based UAV dynamic models and tracking algorithms. This system allows comprehensive simulation and testing of designed control and guidance algorithms before flight tests while minimizing cost and crash risk. We have successfully used the avionics architecture in flight tests that involve (a) system identification of flight vehicles and (b) tracking and identification of signal sources using multiple UAVs.}},
keywords = {unmanned aerial vehicles, avionics, swarm},
doi = {https://doi.org/10.1109/ICMAE52228.2021.9522365}}
[M28]
Hüner, Y., Gayretli, M.G., Yeniçeri, R.,
"HW/SW Design Space Exploration of A Complementary Filter on Zynq SoC,"
8th International Conference on Electrical and Electronics Engineering (ICEEE 2021),
Antalya, Turkey, April 9-11, 2021.
Honored with Best Presentation in Session Award.
@inproceedings{yenicerirM28,
author={Huner, Yakup and Gayretli, Mumin Goker and Yeniceri, Ramazan},
booktitle={2021 8th International Conference on Electrical and Electronics Engineering (ICEEE)},
title={HW/SW Design Space Exploration of A Complementary Filter on Zynq SoC},
year={2021},
month={April},
pages={1-5},
abstract={In this paper, a Complementary Filter (CF) for pitch and roll angle estimation based on linear acceleration and angular rate measurements is designed and implemented on a Xilinx Zynq System-on-Chip (SoC) device. The CF is modelled in Simulink. Its C code and HDL code is generated by the Embedded Coder and the HDL coder, respectively. Filter input and output interface is constituted by a Hardware Abstraction Layer (HAL) which is manually designed and implemented on the Processing Logic (PL) of the SoC. The performance analysis of hardware/software (HW/SW) implementations of the CF is presented aiming realtime operation. The results of dual-core ARM Cortex-A9 Processing System (PS) running the stock PetaLinux kernel is presented with different task priority conditions, CPU loads, and sleep policies. The real-time performance of Linux based designs are compared with the baremetal SW implementation and absolute HW implementation. The timing is conducted on both SW and HW sides in the designs utilizing the PS. Hence, the data transfer overhead between HW and SW is also revealed. A simple adaptive task sleep approach utilizing PL based counter is proposed for CPU utilization efficiency.},
keywords={system-on-chip, {HW/SW} codesign, design space exploration},
doi={https://doi.org/10.1109/ICEEE52452.2021.9415940}}
author={Huner, Yakup and Gayretli, Mumin Goker and Yeniceri, Ramazan},
booktitle={2021 8th International Conference on Electrical and Electronics Engineering (ICEEE)},
title={HW/SW Design Space Exploration of A Complementary Filter on Zynq SoC},
year={2021},
month={April},
pages={1-5},
abstract={In this paper, a Complementary Filter (CF) for pitch and roll angle estimation based on linear acceleration and angular rate measurements is designed and implemented on a Xilinx Zynq System-on-Chip (SoC) device. The CF is modelled in Simulink. Its C code and HDL code is generated by the Embedded Coder and the HDL coder, respectively. Filter input and output interface is constituted by a Hardware Abstraction Layer (HAL) which is manually designed and implemented on the Processing Logic (PL) of the SoC. The performance analysis of hardware/software (HW/SW) implementations of the CF is presented aiming realtime operation. The results of dual-core ARM Cortex-A9 Processing System (PS) running the stock PetaLinux kernel is presented with different task priority conditions, CPU loads, and sleep policies. The real-time performance of Linux based designs are compared with the baremetal SW implementation and absolute HW implementation. The timing is conducted on both SW and HW sides in the designs utilizing the PS. Hence, the data transfer overhead between HW and SW is also revealed. A simple adaptive task sleep approach utilizing PL based counter is proposed for CPU utilization efficiency.},
keywords={system-on-chip, {HW/SW} codesign, design space exploration},
doi={https://doi.org/10.1109/ICEEE52452.2021.9415940}}
[M27]
Yeniçeri, R., Hüner, Y.,
"HW/SW Codesign and Implementation of an IMU Navigation Filter on Zynq SoC with Linux,"
7th International Conference on Electrical and Electronics Engineering (ICEEE 2020),
Antalya, Turkey, April 14-16, 2020.
@inproceedings{yenicerirM27,
author = {Yeniceri, Ramazan and Huner, Yakup},
booktitle = {{2020 7th International Conference on Electrical and Electronics Engineering (ICEEE)}},
title = {{HW/SW Codesign and Implementation of an IMU Navigation Filter on Zynq SoC with Linux}},
year = {2020},
month = {April},
pages = {351-354},
abstract = {{In this paper, a complementary filter for pitch and roll angle estimation based on linear acceleration and angular rate is designed and implemented on a Xilinx Zynq System on Chip (SoC) device. The filter is partitioned into two parts as hardware (HW) and software (SW) as a result of the communication performance analysis of Advanced eXtensible Interface (AXI) bus for a parallel interface in the Programmable Logic (PL) part of the SoC. PetaLinux operates on the Processing System (PS) part of the SoC and runs a C application. PL performs the HW abstraction by transforming serial inputs/outputs with noise rejection filters into memory mapped variables. Real-time test results and SoC utilization results are reported.}},
keywords = {system-on-chip, {Zynq}, {Linux}, filter, {HW/SW} codesign},
doi={https://doi.org/10.1109/ICEEE49618.2020.9102597}}
author = {Yeniceri, Ramazan and Huner, Yakup},
booktitle = {{2020 7th International Conference on Electrical and Electronics Engineering (ICEEE)}},
title = {{HW/SW Codesign and Implementation of an IMU Navigation Filter on Zynq SoC with Linux}},
year = {2020},
month = {April},
pages = {351-354},
abstract = {{In this paper, a complementary filter for pitch and roll angle estimation based on linear acceleration and angular rate is designed and implemented on a Xilinx Zynq System on Chip (SoC) device. The filter is partitioned into two parts as hardware (HW) and software (SW) as a result of the communication performance analysis of Advanced eXtensible Interface (AXI) bus for a parallel interface in the Programmable Logic (PL) part of the SoC. PetaLinux operates on the Processing System (PS) part of the SoC and runs a C application. PL performs the HW abstraction by transforming serial inputs/outputs with noise rejection filters into memory mapped variables. Real-time test results and SoC utilization results are reported.}},
keywords = {system-on-chip, {Zynq}, {Linux}, filter, {HW/SW} codesign},
doi={https://doi.org/10.1109/ICEEE49618.2020.9102597}}
[M26]
Yüksek, B., Saldıran, E., Çetin, A., Yeniçeri, R., İnalhan, G.,
"System Identification and Model-Based Flight Control System Design for an Agile Maneuvering Quadrotor Platform,"
AIAA Scitech 2020 Forum,
p. 1835, Orlando, FL, Jan 6-10, 2020.
@inproceedings{yenicerirM26,
author = {Yuksek, Burak and Saldiran, Emre and Cetin, Aykut and Yeniceri, Ramazan and Inalhan, Gokhan},
title = {{System Identification and Model-Based Flight Control System Design for an Agile Maneuvering Quadrotor Platform}},
booktitle = {{AIAA Scitech 2020 Forum}},
year = {2020},
month = {January},
pages = {1835-1859},
abstract = {{In this paper, we provide a system identification, model stitching and model-based flight control system design methodology for an agile maneuvering quadrotor micro aerial vehicle (MAV) technology demonstrator platform. The proposed MAV is designed to perform agile maneuvers in hover/low-speed and fast forward flight conditions in which significant changes in system dynamics are observed. As such, these significant changes result in considerable loss of performance and precision using classical hover or forward flight model based controller designs. To capture the changing dynamics, we consider an approach which is adapted from the full-scale manned aircraft and rotorcraft domain. Specifically, linear mathematical models of the MAV in hover and forward flight are obtained by using the frequency-domain system identification method and they are validated in time-domain. These point models are stitched with the trim data and quasi-nonlinear mathematical model is generated for simulation purposes. Identified linear models are used in a multi objective optimization based flight control system design approach in which several handling quality specifications are used to optimize the controller parameters. Lateral reposition and longitudinal depart/abort mission task elements from ADS-33E-PRF are scaled-down by using kinematic scaling to evaluate the proposed flight control systems. Position hold, trajectory tracking and aggressiveness analysis are performed, Monte-Carlo simulations and actual flight test results are compared. The results show that the proposed methodology provides high precision and predictable maneuvering control capability over an extensive speed envelope in comparison to classical control techniques. Our current work focuses on i) extension of the flight envelope of the mathematical model and ii) improvement of agile maneuvering capability of the MAV.}},
doi = {https://doi.org/10.2514/6.2020-1835}}
author = {Yuksek, Burak and Saldiran, Emre and Cetin, Aykut and Yeniceri, Ramazan and Inalhan, Gokhan},
title = {{System Identification and Model-Based Flight Control System Design for an Agile Maneuvering Quadrotor Platform}},
booktitle = {{AIAA Scitech 2020 Forum}},
year = {2020},
month = {January},
pages = {1835-1859},
abstract = {{In this paper, we provide a system identification, model stitching and model-based flight control system design methodology for an agile maneuvering quadrotor micro aerial vehicle (MAV) technology demonstrator platform. The proposed MAV is designed to perform agile maneuvers in hover/low-speed and fast forward flight conditions in which significant changes in system dynamics are observed. As such, these significant changes result in considerable loss of performance and precision using classical hover or forward flight model based controller designs. To capture the changing dynamics, we consider an approach which is adapted from the full-scale manned aircraft and rotorcraft domain. Specifically, linear mathematical models of the MAV in hover and forward flight are obtained by using the frequency-domain system identification method and they are validated in time-domain. These point models are stitched with the trim data and quasi-nonlinear mathematical model is generated for simulation purposes. Identified linear models are used in a multi objective optimization based flight control system design approach in which several handling quality specifications are used to optimize the controller parameters. Lateral reposition and longitudinal depart/abort mission task elements from ADS-33E-PRF are scaled-down by using kinematic scaling to evaluate the proposed flight control systems. Position hold, trajectory tracking and aggressiveness analysis are performed, Monte-Carlo simulations and actual flight test results are compared. The results show that the proposed methodology provides high precision and predictable maneuvering control capability over an extensive speed envelope in comparison to classical control techniques. Our current work focuses on i) extension of the flight envelope of the mathematical model and ii) improvement of agile maneuvering capability of the MAV.}},
doi = {https://doi.org/10.2514/6.2020-1835}}
[M25]
Yüksek, B., Saldıran, E., Çetin, A., Yeniçeri, R., İnalhan, G.,
"A Model Based Flight Control System Design Approach for Micro Aerial Vehicle Using Integrated Flight Testing and HIL Simulation,"
AIAA Scitech 2019 Forum,
p. 1480, San Diego, CA, Jan 7-11, 2019.
@inproceedings{yenicerirM25,
author = {Yuksek, Burak and Saldiran, Emre and Cetin, Aykut and Yeniceri, Ramazan and Inalhan, Gokhan},
title = {{A Model Based Flight Control System Design Approach for Micro Aerial Vehicle Using Integrated Flight Testing and HIL Simulation}},
booktitle = {{AIAA Scitech 2019 Forum}},
year = {2019},
month = {January},
pages = {1480-1505},
abstract = {{In this paper, a model-based flight control system design approach is proposed for a micro aerial vehicle (MAV) using integrated flight testing and hardware-in-the-loop (HIL) simulation. This approach relies on adaptation of system identification and control system design methodologies from the manned aircraft domain. The MAV is specifically designed for a surveillance mission in which a moving ground target such as a ship or a boat is tracked fully autonomously from a specified altitude by using a downward facing camera. We utilize a design process in which the longitudinal and lateral mathematical models are identified through open-loop system identification flight testing. These models are later used in a multi-objective controller optimization scheme in which a control system is designed inline with the high performance tracking requirements. We have utilized a hardware-in- the-loop simulation system allowing comprehensive simulation and testing of designed control and guidance algorithms before fully autonomous flight tests as to minimize cost and crash risk. Both the designed control system and also the legacy flight control system of the autopilot are flight tested. The results demonstrate that the proposed methodology and the resulting control system provides higher performance and robust disturbance rejection in face of real-world conditions such as turbulence and winds.}},
doi = {https://doi.org/10.2514/6.2019-1480}}
author = {Yuksek, Burak and Saldiran, Emre and Cetin, Aykut and Yeniceri, Ramazan and Inalhan, Gokhan},
title = {{A Model Based Flight Control System Design Approach for Micro Aerial Vehicle Using Integrated Flight Testing and HIL Simulation}},
booktitle = {{AIAA Scitech 2019 Forum}},
year = {2019},
month = {January},
pages = {1480-1505},
abstract = {{In this paper, a model-based flight control system design approach is proposed for a micro aerial vehicle (MAV) using integrated flight testing and hardware-in-the-loop (HIL) simulation. This approach relies on adaptation of system identification and control system design methodologies from the manned aircraft domain. The MAV is specifically designed for a surveillance mission in which a moving ground target such as a ship or a boat is tracked fully autonomously from a specified altitude by using a downward facing camera. We utilize a design process in which the longitudinal and lateral mathematical models are identified through open-loop system identification flight testing. These models are later used in a multi-objective controller optimization scheme in which a control system is designed inline with the high performance tracking requirements. We have utilized a hardware-in- the-loop simulation system allowing comprehensive simulation and testing of designed control and guidance algorithms before fully autonomous flight tests as to minimize cost and crash risk. Both the designed control system and also the legacy flight control system of the autopilot are flight tested. The results demonstrate that the proposed methodology and the resulting control system provides higher performance and robust disturbance rejection in face of real-world conditions such as turbulence and winds.}},
doi = {https://doi.org/10.2514/6.2019-1480}}
[M24]
Herekoğlu, Ö., Hasanzade, M., Saldıran, E., Çetin, A., Özgür, İ., Küçükoğlu, A.G., Üstün, M.B., Yüksek, B., Yeniçeri, R., Koyuncu, E., İnalhan, G.,
"Flight Testing of a Multiple UAV RF Emission and Vision Based Target Localization Method,"
AIAA Scitech 2019 Forum,
p. 1570, San Diego, CA, Jan 7-11, 2019.
@inproceedings{yenicerirM24,
author = {Herekoglu, Omer and Hasanzade, Mehmet and Saldiran, Emre and Cetin, Aykut and Ozgur, Irem and Kucukoglu, Abdulkadir Geylani and Ustun, Mehmet Burak and Yuksek, Burak and Yeniceri, Ramazan and Koyuncu, Emre and Inalhan, Gokhan},
title = {{Flight Testing of a Multiple UAV RF Emission and Vision Based Target Localization Method}},
booktitle = {{AIAA Scitech 2019 Forum}},
year = {2019},
month = {January},
pages = {1570-1587},
abstract = {{In this paper, we present the flight tests of a solution for finding and localizing a radio frequency emitting target using multiple autonomous unmanned aerial vehicles. The method relies on Particle Filter and Extended Kalman Filter algorithms based on signal strength tracking. After estimation, vision-based detection is used in order to improve the localization. The proposed solution is first tested on an in-house developed software-in-the-loop system and then, radio frequency signal strength measurement tests and vision-based object detection tests are conducted in flight tests. Outdoor flight tests are performed and the results are presented with designed hardware and software architectures. The proposed solution meets of all operational requirements for the localization and the detection of the target.}},
doi = {https://doi.org/10.2514/6.2019-1570}}
author = {Herekoglu, Omer and Hasanzade, Mehmet and Saldiran, Emre and Cetin, Aykut and Ozgur, Irem and Kucukoglu, Abdulkadir Geylani and Ustun, Mehmet Burak and Yuksek, Burak and Yeniceri, Ramazan and Koyuncu, Emre and Inalhan, Gokhan},
title = {{Flight Testing of a Multiple UAV RF Emission and Vision Based Target Localization Method}},
booktitle = {{AIAA Scitech 2019 Forum}},
year = {2019},
month = {January},
pages = {1570-1587},
abstract = {{In this paper, we present the flight tests of a solution for finding and localizing a radio frequency emitting target using multiple autonomous unmanned aerial vehicles. The method relies on Particle Filter and Extended Kalman Filter algorithms based on signal strength tracking. After estimation, vision-based detection is used in order to improve the localization. The proposed solution is first tested on an in-house developed software-in-the-loop system and then, radio frequency signal strength measurement tests and vision-based object detection tests are conducted in flight tests. Outdoor flight tests are performed and the results are presented with designed hardware and software architectures. The proposed solution meets of all operational requirements for the localization and the detection of the target.}},
doi = {https://doi.org/10.2514/6.2019-1570}}
[M23]
Akçakoca, M., Atıcı, B.M., Gever, B., Oğuz, S., Demirezen, U., Demir, M., Saldıran, E., Yüksek, B., Koyuncu, E., Yeniçeri, R., İnalhan, G.,
"A Simulation-Based Development and Verification Architecture for Micro UAV Teams and Swarms,"
AIAA Scitech 2019 Forum,
p. 1979, San Diego, CA, Jan 7-11, 2019.
@inproceedings{yenicerirM23,
author = {Akcakoca, Mehmet and Atici, Bilge Mirac and Gever, Basak and Oguz, Sinan and Demirezen, Umut and Demir, Mustafa and Saldiran, Emre and Yuksek, Burak and Koyuncu, Emre and Yeniceri, Ramazan and Inalhan, Gokhan},
title = {{A Simulation-Based Development and Verification Architecture for Micro UAV Teams and Swarms}},
booktitle = {{AIAA Scitech 2019 Forum}},
year = {2019},
month = {January},
pages = {1979-1993},
abstract = {{In this work, we present an unmanned aerial vehicle (UAV) simulation-based, hardware and software development and verification architecture structured around the Robot Operating System (ROS). One of the key expectations of such a system is a graceful increase in architectural and computational complexity as the number of vehicles and vehicle complexity increases. In addition, the system is expected to provide the ability to test and verify algorithms both at the software and hardware level before real flight operations. This requirement also couples with the requested flexibility of updating the models and the algorithms based on the results coming from real operations. As such, the designed architecture allows joint simulation and testing at both hardware and software layers for multiple vehicle and swarm operations. Specifically, the architecture consists of distinct and networked layers where hardware elements such as autopilot systems (e.g., Pixhawk, Ardupilot etc.), ground stations and external motion capture/localization systems (e.g., Vicon, Otus Tracker etc.) are integrated around the ROS simulation shell. In addition, the dynamics, sensor models, motion planning and other features can be driven by highly parallel MATLAB/Simulink models. Visualization and visual sensing is obtained through linking of virtual reality with simulation environments such as Gazebo and Airsim. This highly reconfigurable architecture allows research teams to work on multidisciplinary areas such as modeling, control, computer vision, artificial intelligence and machine learning within the same simulation and test environment.}},
doi = {https://doi.org/10.2514/6.2019-1979}}
author = {Akcakoca, Mehmet and Atici, Bilge Mirac and Gever, Basak and Oguz, Sinan and Demirezen, Umut and Demir, Mustafa and Saldiran, Emre and Yuksek, Burak and Koyuncu, Emre and Yeniceri, Ramazan and Inalhan, Gokhan},
title = {{A Simulation-Based Development and Verification Architecture for Micro UAV Teams and Swarms}},
booktitle = {{AIAA Scitech 2019 Forum}},
year = {2019},
month = {January},
pages = {1979-1993},
abstract = {{In this work, we present an unmanned aerial vehicle (UAV) simulation-based, hardware and software development and verification architecture structured around the Robot Operating System (ROS). One of the key expectations of such a system is a graceful increase in architectural and computational complexity as the number of vehicles and vehicle complexity increases. In addition, the system is expected to provide the ability to test and verify algorithms both at the software and hardware level before real flight operations. This requirement also couples with the requested flexibility of updating the models and the algorithms based on the results coming from real operations. As such, the designed architecture allows joint simulation and testing at both hardware and software layers for multiple vehicle and swarm operations. Specifically, the architecture consists of distinct and networked layers where hardware elements such as autopilot systems (e.g., Pixhawk, Ardupilot etc.), ground stations and external motion capture/localization systems (e.g., Vicon, Otus Tracker etc.) are integrated around the ROS simulation shell. In addition, the dynamics, sensor models, motion planning and other features can be driven by highly parallel MATLAB/Simulink models. Visualization and visual sensing is obtained through linking of virtual reality with simulation environments such as Gazebo and Airsim. This highly reconfigurable architecture allows research teams to work on multidisciplinary areas such as modeling, control, computer vision, artificial intelligence and machine learning within the same simulation and test environment.}},
doi = {https://doi.org/10.2514/6.2019-1979}}
[M22]
Hasanzade, M., Herekoğlu, Ö., Yeniçeri, R., Koyuncu, E., İnalhan, G.,
"RF Source Localization using Unmanned Aerial Vehicle with Particle Filter,"
The 9-th International Conference on Mechanical and Aerospace Engineering (ICMAE 2018),
Budapest, Hungary, July 10-13, 2018.
@inproceedings{yenicerirM22,
author = {Hasanzade, Mehmet and Herekoglu, Omer and Yeniceri, Ramazan and Koyuncu, Emre and Inalhan, Gokhan},
booktitle = {{2018 9th International Conference on Mechanical and Aerospace Engineering (ICMAE)}},
title = {{RF Source Localization using Unmanned Aerial Vehicle with Particle Filter}},
month = {July},
year = {2018},
pages = {284-289},
abstract = {{In this paper, we propose a solution for the localization problem of a radio frequency (RF) emitting source over a large scale environment with unmanned aerial vehicle (UAV). Target localization using received signal strength indicator(RSSI) is one of the most challenging problem because of noise characteristics. To evaluate the noise effect on RSSI, we perform a RSSI measurement test. This adds value for proper model and helps to implement a more realistic simulation system. For the localization process, the particle filter is utilized in this paper instead of tools such as Extended Kalman Filter with multi UAVs. Simulation environment and software-in-the-loop system are prepared to exhibit the conceptual proof with realistic models and autopilot system. Simulation results show that, mean search time for localization is 84.06 seconds and mean distance error is 13.96 meters.}},
keywords = {{RSSI}, particle filter, {RF}, {UAV}, localization},
doi = {https://doi.org/10.1109/ICMAE.2018.8467555}}
author = {Hasanzade, Mehmet and Herekoglu, Omer and Yeniceri, Ramazan and Koyuncu, Emre and Inalhan, Gokhan},
booktitle = {{2018 9th International Conference on Mechanical and Aerospace Engineering (ICMAE)}},
title = {{RF Source Localization using Unmanned Aerial Vehicle with Particle Filter}},
month = {July},
year = {2018},
pages = {284-289},
abstract = {{In this paper, we propose a solution for the localization problem of a radio frequency (RF) emitting source over a large scale environment with unmanned aerial vehicle (UAV). Target localization using received signal strength indicator(RSSI) is one of the most challenging problem because of noise characteristics. To evaluate the noise effect on RSSI, we perform a RSSI measurement test. This adds value for proper model and helps to implement a more realistic simulation system. For the localization process, the particle filter is utilized in this paper instead of tools such as Extended Kalman Filter with multi UAVs. Simulation environment and software-in-the-loop system are prepared to exhibit the conceptual proof with realistic models and autopilot system. Simulation results show that, mean search time for localization is 84.06 seconds and mean distance error is 13.96 meters.}},
keywords = {{RSSI}, particle filter, {RF}, {UAV}, localization},
doi = {https://doi.org/10.1109/ICMAE.2018.8467555}}
[M21]
Akçay, L., Çil, E., Vardar, A., Yaman, İ., Yeniçeri, R., Yalçın, M.E.,
"Implementation of a Chaotic Time-Delay RNG Based Secure Communication System on FPGA,"
10th International Conference on Electrical and Electronics Engineering (ELECO 2017),
Bursa, Turkey, November 30-December 2, 2017.
@inproceedings{yenicerirM21,
author = {Akcay, Latif and Cil, Erdem and Vardar, Alptekin and Yaman, Ilayda and Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{Implementation of a Chaotic Time-Delay RNG Based Secure Communication System on FPGA}},
booktitle = {{2017 10th International Conference on Electrical and Electronics Engineering (ELECO)}},
year = {2017},
month = {November},
pages = {1277-1280},
abstract = {{Security is one of the most important design parameters in communication systems. Security of cryptographic systems depends on the unpredictability of keys. Chaotic random number generators have become an alternative method for random number generation instead of physical noise based ones. In this work, we describe a system-on-chip design which includes a chaos-based random number generator. Key generation, encryption-decryption blocks and control unit are designed to run on the same chip. All blocks are connected to the Microblaze softcore processor and implemented on a Xilinx FPGA. Structural details of the system and the results are shared.}},
keywords = {chaotic communication, generators, encryption, clocks, delay lines},
url = {https://ieeexplore.ieee.org/document/8266252/}}
author = {Akcay, Latif and Cil, Erdem and Vardar, Alptekin and Yaman, Ilayda and Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{Implementation of a Chaotic Time-Delay RNG Based Secure Communication System on FPGA}},
booktitle = {{2017 10th International Conference on Electrical and Electronics Engineering (ELECO)}},
year = {2017},
month = {November},
pages = {1277-1280},
abstract = {{Security is one of the most important design parameters in communication systems. Security of cryptographic systems depends on the unpredictability of keys. Chaotic random number generators have become an alternative method for random number generation instead of physical noise based ones. In this work, we describe a system-on-chip design which includes a chaos-based random number generator. Key generation, encryption-decryption blocks and control unit are designed to run on the same chip. All blocks are connected to the Microblaze softcore processor and implemented on a Xilinx FPGA. Structural details of the system and the results are shared.}},
keywords = {chaotic communication, generators, encryption, clocks, delay lines},
url = {https://ieeexplore.ieee.org/document/8266252/}}
[M20]
Abtioğlu, E., Yeniçeri, R., Gövem, B., Göncü, E., Yalçın, M.E.,
"Partially Reconfigurable IP Protection System with Ring Oscillator Based Physically Unclonable Functions,"
Proc. of First New Generation of Circuits and Systems Conference (NGCAS 2017),
Genova, Italy, September 7-9, 2017.
@inproceedings{yenicerirM20,
author = {Abtioglu, Emrah and Yeniceri, Ramazan and Govem, Burak and Goncu, Emre and Yalcin, Mustak Erhan and Saldamli, Gokay},
booktitle = {{2017 New Generation of CAS (NGCAS)}},
title = {{Partially Reconfigurable IP Protection System with Ring Oscillator Based Physically Unclonable Functions}},
year = {2017},
month = {September},
pages = {65-68},
abstract = {{The size of counterfeiting activities is increasing day by day. These activities are encountered especially in electronics market. In this paper, a countermeasure against counterfeiting on intellectual properties (IP) on Field-Programmable Gate Arrays (FPGA) is proposed. FPGA vendors provide bitstream ciphering as an IP security solution such as battery-backed or non-volatile FPGAs. However, these solutions are secure as long as they can keep decryption key away from third parties. Key storage and key transfer over unsecure channels expose risks for these solutions. In this work, physical unclonable functions (PUFs) have been used for key generation. Generating a key from a circuit in the device solves key transfer problem. Proposed system goes through different phases when it operates. Therefore, partial reconfiguration feature of FPGAs is essential for feasibility of proposed system.}},
keywords = {{IP} protection, physical unclonable functions, partial reconfiguration, {FPGAs}, hardware security},
doi = {https://doi.org/10.1109/NGCAS.2017.66}}
author = {Abtioglu, Emrah and Yeniceri, Ramazan and Govem, Burak and Goncu, Emre and Yalcin, Mustak Erhan and Saldamli, Gokay},
booktitle = {{2017 New Generation of CAS (NGCAS)}},
title = {{Partially Reconfigurable IP Protection System with Ring Oscillator Based Physically Unclonable Functions}},
year = {2017},
month = {September},
pages = {65-68},
abstract = {{The size of counterfeiting activities is increasing day by day. These activities are encountered especially in electronics market. In this paper, a countermeasure against counterfeiting on intellectual properties (IP) on Field-Programmable Gate Arrays (FPGA) is proposed. FPGA vendors provide bitstream ciphering as an IP security solution such as battery-backed or non-volatile FPGAs. However, these solutions are secure as long as they can keep decryption key away from third parties. Key storage and key transfer over unsecure channels expose risks for these solutions. In this work, physical unclonable functions (PUFs) have been used for key generation. Generating a key from a circuit in the device solves key transfer problem. Proposed system goes through different phases when it operates. Therefore, partial reconfiguration feature of FPGAs is essential for feasibility of proposed system.}},
keywords = {{IP} protection, physical unclonable functions, partial reconfiguration, {FPGAs}, hardware security},
doi = {https://doi.org/10.1109/NGCAS.2017.66}}
[M19]
Yeniçeri, R., Vardar, A., Çil, E., Akçay, L., Göncü, E., Yalçın, M.E.,
"A Chaotic Time-delay System Based Digital RNG and Integrated Autonomous Test Suite,"
Proc. of European Conference on Circuit Theory and Design 2017 (ECCTD 2017),
Catania, Italy, September 4-6, 2017.
@inproceedings{yenicerirM19,
author = {Yeniceri, Ramazan and Vardar, Alptekin and Cil, Erdem and Akcay, Latif and Goncu, Emre and Yalcin, Mustak Erhan},
title = {{A Chaotic Time-delay System Based Digital RNG and Integrated Autonomous Test Suite}},
booktitle = {{2017 European Conference on Circuit Theory and Design (ECCTD)}},
year = {2017},
month = {September},
pages = {1-4},
abstract = {{This paper presents a time-delay system which originally has chaotic behavior, yet lost that dynamic due to finite quantization levels of state variable representation. One method to overcome this destructive effect of digitalization is engaging a time-varying delay amount which is studied in this paper. Based on this system, random number generator (RNG) topologies are demonstrated with better throughput values in comparison with our previous implementations. Online performance monitoring ability is integrated to the RNG for a further investigation on physical implementation variations. The results related to the implementation area variation and target Field-Programmable Gate Array (FPGA) chip variation are reported and discussed. The initial findings promise an advanced usage of proposed RNGs as Physically Unclonnable Function (PUF).}},
keywords = {chaos, delays, field programmable gate arrays, random number generation},
doi = {https://doi.org/10.1109/ECCTD.2017.8093272}}
author = {Yeniceri, Ramazan and Vardar, Alptekin and Cil, Erdem and Akcay, Latif and Goncu, Emre and Yalcin, Mustak Erhan},
title = {{A Chaotic Time-delay System Based Digital RNG and Integrated Autonomous Test Suite}},
booktitle = {{2017 European Conference on Circuit Theory and Design (ECCTD)}},
year = {2017},
month = {September},
pages = {1-4},
abstract = {{This paper presents a time-delay system which originally has chaotic behavior, yet lost that dynamic due to finite quantization levels of state variable representation. One method to overcome this destructive effect of digitalization is engaging a time-varying delay amount which is studied in this paper. Based on this system, random number generator (RNG) topologies are demonstrated with better throughput values in comparison with our previous implementations. Online performance monitoring ability is integrated to the RNG for a further investigation on physical implementation variations. The results related to the implementation area variation and target Field-Programmable Gate Array (FPGA) chip variation are reported and discussed. The initial findings promise an advanced usage of proposed RNGs as Physically Unclonnable Function (PUF).}},
keywords = {chaos, delays, field programmable gate arrays, random number generation},
doi = {https://doi.org/10.1109/ECCTD.2017.8093272}}
[M18]
Hasanzade, M., Herekoğlu, Ö., Üre, N.K., Koyuncu, E., Yeniçeri, R., İnalhan, G.,
"Localization and Tracking of RF Emitting Targets with Multiple Unmanned Aerial Vehicles in Large Scale Environments with Uncertain Transmitter Power,"
The 2017 International Conference on Unmanned Aircraft Systems (ICUAS'17),
Biscayne Bay, Miami, FL, June 13-16, 2017.
@inproceedings{yenicerirM18,
author = {Hasanzade, Mehmet and Herekoglu, Omer and Ure, Nazim Kemal and Koyuncu, Emre and Yeniceri, Ramazan and Inalhan, Gokhan},
title = {{Localization and Tracking of RF Emitting Targets with Multiple Unmanned Aerial Vehicles in Large Scale Environments with Uncertain Transmitter Power}},
booktitle = {{2017 International Conference on Unmanned Aircraft Systems (ICUAS)}},
year = {2017},
month = {June},
pages = {1058-1065},
abstract = {{In this paper we study the localization and tracking of a radio frequency (RF) emitting target using multiple unmanned aerial vehicles (UAVs) over a large scale environment. Although localization of RF emitting targets using multiple measurements is a well studied problem, the standard approaches become inefficient when the signal power is uncertain and there is significant noise in the received signal strength (RSS) when the search environment is large scale. We present a localization and tracking architecture, where a data driven neural network model is used for estimating the unknown signal strength and extended Kalman filters are utilized for eliminating the RSS noise and increase the precision of target tracking performance. We present simulation results in a 10 × 10 km2 search area, where 3 fixed wing UAVs localize and track a target with up to 28.3 m average error distance.}},
keywords = {autonomous aerial vehicles, {Kalman} filters, radio equipment, target tracking},
doi = {https://doi.org/10.1109/ICUAS.2017.7991409}}
author = {Hasanzade, Mehmet and Herekoglu, Omer and Ure, Nazim Kemal and Koyuncu, Emre and Yeniceri, Ramazan and Inalhan, Gokhan},
title = {{Localization and Tracking of RF Emitting Targets with Multiple Unmanned Aerial Vehicles in Large Scale Environments with Uncertain Transmitter Power}},
booktitle = {{2017 International Conference on Unmanned Aircraft Systems (ICUAS)}},
year = {2017},
month = {June},
pages = {1058-1065},
abstract = {{In this paper we study the localization and tracking of a radio frequency (RF) emitting target using multiple unmanned aerial vehicles (UAVs) over a large scale environment. Although localization of RF emitting targets using multiple measurements is a well studied problem, the standard approaches become inefficient when the signal power is uncertain and there is significant noise in the received signal strength (RSS) when the search environment is large scale. We present a localization and tracking architecture, where a data driven neural network model is used for estimating the unknown signal strength and extended Kalman filters are utilized for eliminating the RSS noise and increase the precision of target tracking performance. We present simulation results in a 10 × 10 km2 search area, where 3 fixed wing UAVs localize and track a target with up to 28.3 m average error distance.}},
keywords = {autonomous aerial vehicles, {Kalman} filters, radio equipment, target tracking},
doi = {https://doi.org/10.1109/ICUAS.2017.7991409}}
[M17]
Yeniçeri, R., Vardar, A., Yalçın, M.E.,
"Full Digital Implementation of A Chaotic Time-delay Sampled-data System,"
IEEE International Symposium on Circuits and Systems (ISCAS 2017),
Baltimore, MD, May 28-31, 2017.
@inproceedings{yenicerirM17,
author = {Yeniceri, Ramazan and Vardar, Alptekin and Yalcin, Mustak Erhan},
title = {{Full Digital Implementation of A Chaotic Time-delay Sampled-data System}},
booktitle = {{IEEE International Symposium on Circuits and Systems (ISCAS 2017)}},
year = {2017},
month = {May},
pages = {1-4},
abstract = {{Chaos-based RNGs have become an alternative method for random number generation (RNG) which is the vital part of the security hardware. When full-digital implementations of a chaotic system are considered, a periodic limit cycle with a large period appears. In order to reverse this degradation in dynamics of chaotic time-delay sampled system, the digital circuit has been supported by delaying buffers which utilize the jitter to break the periodic motion. Thus, the a periodic behavior of proposed full digital design resembles the original chaotic behavior. Designs of the system are tested on a field-programmable gate array (FPGA). Furthermore, two RNGs based on these designs are given and test results are presented in the paper. Tests indicate that when time-varying delay is included using propagation delay even 8-bit representation of the system shows the sensitive dependence on initial conditions.}},
doi = {https://doi.org/10.1109/ISCAS.2017.8050862}}
author = {Yeniceri, Ramazan and Vardar, Alptekin and Yalcin, Mustak Erhan},
title = {{Full Digital Implementation of A Chaotic Time-delay Sampled-data System}},
booktitle = {{IEEE International Symposium on Circuits and Systems (ISCAS 2017)}},
year = {2017},
month = {May},
pages = {1-4},
abstract = {{Chaos-based RNGs have become an alternative method for random number generation (RNG) which is the vital part of the security hardware. When full-digital implementations of a chaotic system are considered, a periodic limit cycle with a large period appears. In order to reverse this degradation in dynamics of chaotic time-delay sampled system, the digital circuit has been supported by delaying buffers which utilize the jitter to break the periodic motion. Thus, the a periodic behavior of proposed full digital design resembles the original chaotic behavior. Designs of the system are tested on a field-programmable gate array (FPGA). Furthermore, two RNGs based on these designs are given and test results are presented in the paper. Tests indicate that when time-varying delay is included using propagation delay even 8-bit representation of the system shows the sensitive dependence on initial conditions.}},
doi = {https://doi.org/10.1109/ISCAS.2017.8050862}}
[M16]
Yeniçeri, R., Hasanzade, M., Koyuncu, E., İnalhan, G.,
"Enabling Centralized UTM Services through Cellular Network for VLL UAVs,"
17th Integrated Communications, Navigation and Surveillance Systems (ICNS) Conference,
Westin Washington Dulles Airport, Herndon, VA, April 18-20, 2017.
Honored with Best Paper in Session Award.
@inproceedings{yenicerirM16,
author = {Yeniceri, Ramazan and Hasanzade, Mehmet and Koyuncu, Emre and Inalhan, Gokhan},
title = {{Enabling Centralized UTM Services through Cellular Network for VLL UAVs}},
booktitle = {{17th Integrated Communications, Navigation and Surveillance Systems (ICNS) Conference}},
year = {2017},
month = {April},
pages = {2E1.1-2E1.13},
abstract = {{In this work, we present a low-cost small onboard Unmanned Aircraft System Traffic Management (UTM) concept allowing Very Low Level (VLL) Unmanned Aerial Vehicle (UAV) operators to access to a various type of centralized services such as e-identification, flight tracking, dynamic geo-fencing and automated flight restriction/permission with multi-level link redundancy that meets the requirements of future flight operations for small UAVs. The presented lowcost system provides ADS-B-like positional information broadcasting through the cellular network (i.e. 3G, 4G or LTE) out-link, which makes small UAVs visible for traffic controllers and other operators enabling continuous tracking and collaborative sense-and-avoid. The system further provides short-range information broadcasting, which uses standardized 63-byte data frame, through a wireless link for multi-level redundancy.}},
doi = {https://doi.org/10.1109/ICNSURV.2017.8011906}}
author = {Yeniceri, Ramazan and Hasanzade, Mehmet and Koyuncu, Emre and Inalhan, Gokhan},
title = {{Enabling Centralized UTM Services through Cellular Network for VLL UAVs}},
booktitle = {{17th Integrated Communications, Navigation and Surveillance Systems (ICNS) Conference}},
year = {2017},
month = {April},
pages = {2E1.1-2E1.13},
abstract = {{In this work, we present a low-cost small onboard Unmanned Aircraft System Traffic Management (UTM) concept allowing Very Low Level (VLL) Unmanned Aerial Vehicle (UAV) operators to access to a various type of centralized services such as e-identification, flight tracking, dynamic geo-fencing and automated flight restriction/permission with multi-level link redundancy that meets the requirements of future flight operations for small UAVs. The presented lowcost system provides ADS-B-like positional information broadcasting through the cellular network (i.e. 3G, 4G or LTE) out-link, which makes small UAVs visible for traffic controllers and other operators enabling continuous tracking and collaborative sense-and-avoid. The system further provides short-range information broadcasting, which uses standardized 63-byte data frame, through a wireless link for multi-level redundancy.}},
doi = {https://doi.org/10.1109/ICNSURV.2017.8011906}}
[M15]
Csaba, G., Papp, Á., Yeniçeri, R., Porod, W.,
"Non-Boolean Computing Based on Linear Waves and Oscillators,"
45th European Solid-State Device Conference,
Graz, Austria, September 14-18, 2015.
@inproceedings{yenicerirM15,
author = {Csaba, Gyorgy and Papp, Adam and Porod, Wolfgang and Yeniceri, Ramazan},
title = {{Non-Boolean Computing Based on Linear Waves and Oscillators}},
booktitle = {{2015 45th European Solid State Device Research Conference (ESSDERC)}},
year = {2015},
month = {September},
pages = {101-104},
abstract = {{We investigate, how linear or weakly nonlinear oscillatory systems (coupled nanoscale oscillators and propagating spin-waves) can be used as non-Boolean computing systems. We study two model systems: nearest-neighbor connected harmonic oscillators and propagating spin-waves. We argue that these systems may realize efficient co-processors for some demanding applications (image processing, associative memories, scientific computations), where digital CMOS solutions are notably inefficient. Wave-based processing architectures may use emerging nano-scale oscillators as device components, potentially surpassing end-of-roadmap CMOS performance.}},
doi = {https://doi.org/10.1109/ESSDERC.2015.7324723}}
author = {Csaba, Gyorgy and Papp, Adam and Porod, Wolfgang and Yeniceri, Ramazan},
title = {{Non-Boolean Computing Based on Linear Waves and Oscillators}},
booktitle = {{2015 45th European Solid State Device Research Conference (ESSDERC)}},
year = {2015},
month = {September},
pages = {101-104},
abstract = {{We investigate, how linear or weakly nonlinear oscillatory systems (coupled nanoscale oscillators and propagating spin-waves) can be used as non-Boolean computing systems. We study two model systems: nearest-neighbor connected harmonic oscillators and propagating spin-waves. We argue that these systems may realize efficient co-processors for some demanding applications (image processing, associative memories, scientific computations), where digital CMOS solutions are notably inefficient. Wave-based processing architectures may use emerging nano-scale oscillators as device components, potentially surpassing end-of-roadmap CMOS performance.}},
doi = {https://doi.org/10.1109/ESSDERC.2015.7324723}}
[M14]
Abtioğlu, E., Yeniçeri, R., Yalçın, M.E.,
"Cellular Network of Networks on Dynamically Partial Reconfigurable FPGA,"
Proc. of 22nd European Conference on Circuit Theory and Design (ECCTD2015),
Trondheim, Norway, August 24-26, 2015.
@inproceedings{yenicerirM14,
author = {Abtioglu, Emrah and Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{Cellular Network of Networks on Dynamically Partial Reconfigurable FPGA}},
booktitle = {{2015 European Conference on Circuit Theory and Design (ECCTD)}},
year = {2015},
month = {August},
pages = {1-4},
abstract = {{Nowadays, Dynamic Partial Reconfiguration of digital circuits like Field-Programmable Gate Arrays (FPGA) appears as a sustainable hardware evolution phenomenon. Like many other architectures, Cellular Nonlinear Networks (CNN) are able to be adjusted or reprogrammed, when the characteristics of the problem are changed. Currently, changing memory content like parameters effects only the operation of architecture which has all functions, including momentarily redundant ones. The appeared question is how the overhead created by functional redundancy of hardware can be decreased. As discussed and studied in this paper, hardware pieces can be reconfigured to completely different designs when the characteristic of the problem is changed in run-time. The paper aims to exhibit the benefits of Dynamic Partial Reconfiguration feature of contemporary FPGAs on CNNs varying/evolving in time under the Network of Networks concept. For this purpose, trigger-wave generating subnetworks are combined using different reconfigurable partitions of an FPGA and a primary network is constituted which generates different trigger-wave patterns. This conceptual design unrolls how dynamic partial reconfiguration is capable to realize irregular/asymmetric network components.}},
doi = {https://doi.org/10.1109/ECCTD.2015.7300002}}
author = {Abtioglu, Emrah and Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{Cellular Network of Networks on Dynamically Partial Reconfigurable FPGA}},
booktitle = {{2015 European Conference on Circuit Theory and Design (ECCTD)}},
year = {2015},
month = {August},
pages = {1-4},
abstract = {{Nowadays, Dynamic Partial Reconfiguration of digital circuits like Field-Programmable Gate Arrays (FPGA) appears as a sustainable hardware evolution phenomenon. Like many other architectures, Cellular Nonlinear Networks (CNN) are able to be adjusted or reprogrammed, when the characteristics of the problem are changed. Currently, changing memory content like parameters effects only the operation of architecture which has all functions, including momentarily redundant ones. The appeared question is how the overhead created by functional redundancy of hardware can be decreased. As discussed and studied in this paper, hardware pieces can be reconfigured to completely different designs when the characteristic of the problem is changed in run-time. The paper aims to exhibit the benefits of Dynamic Partial Reconfiguration feature of contemporary FPGAs on CNNs varying/evolving in time under the Network of Networks concept. For this purpose, trigger-wave generating subnetworks are combined using different reconfigurable partitions of an FPGA and a primary network is constituted which generates different trigger-wave patterns. This conceptual design unrolls how dynamic partial reconfiguration is capable to realize irregular/asymmetric network components.}},
doi = {https://doi.org/10.1109/ECCTD.2015.7300002}}
[M13]
Yeniçeri, R., Yalçın, M.E.,
"Anticipating Synchronization Between Sampled-Time Master And Discrete-Time Slave Chaotic Systems,"
7th International Scientific Conference on Physics and Control (PhysCon 2015),
Istanbul, Turkey, August 19-22, 2015.
@inproceedings{yenicerirM13,
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{Anticipating Synchronization Between Sampled-Time Master and Discrete-Time Slave Chaotic Systems}},
booktitle = {{7th International Scientific Conference on Physics and Control (PhysCon 2015)}},
year = {2015},
month = {August},
pages = {1-4},
abstract = {{The anticipating synchronization between time-delay systems is studied with a sampled-data master and discrete-time slave systems in this paper. The rough discrete-time approximation of the original sampled-data system exhibits significant performance when locking to the master system and generating the anticipated signal. System models, coupling schemes, error bound, block diagram of the implemented system are presented with the phase portraits and signal plots in time. The proposed anticipation method by simple discrete-time slave systems enables to use hundreds of slave systems which promises to anticipate the chaotic signal hundreds of τ beforehand using a single digital chip.}},
keywords = {anticipating, synchronization, chaos, delay},
url = {http://lib.physcon.ru/doc?id=14c75dd14b64}}
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{Anticipating Synchronization Between Sampled-Time Master and Discrete-Time Slave Chaotic Systems}},
booktitle = {{7th International Scientific Conference on Physics and Control (PhysCon 2015)}},
year = {2015},
month = {August},
pages = {1-4},
abstract = {{The anticipating synchronization between time-delay systems is studied with a sampled-data master and discrete-time slave systems in this paper. The rough discrete-time approximation of the original sampled-data system exhibits significant performance when locking to the master system and generating the anticipated signal. System models, coupling schemes, error bound, block diagram of the implemented system are presented with the phase portraits and signal plots in time. The proposed anticipation method by simple discrete-time slave systems enables to use hundreds of slave systems which promises to anticipate the chaotic signal hundreds of τ beforehand using a single digital chip.}},
keywords = {anticipating, synchronization, chaos, delay},
url = {http://lib.physcon.ru/doc?id=14c75dd14b64}}
[M12]
Karakaya, B., Yeniçeri, R., Yalçın, M.E.,
"Wave Computer Core Using Fixed-point Arithmetic,"
Proc. of Circuits and Systems (ISCAS), 2015 IEEE International Symposium on,
pp. 1514 - 1517, Lisbon, Portugal, May 24–27, 2015.
@inproceedings{yenicerirM12,
author = {Karakaya, Baris and Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{Wave Computer Core Using Fixed-point Arithmetic}},
booktitle = {{2015 IEEE International Symposium on Circuits and Systems (ISCAS)}},
year = {2015},
month = {May},
pages = {1514-1517},
abstract = {{In this paper, success on cellular nonlinear network emulator core that generates active waves such as autowaves and traveling waves is intended. This wave computer core has 4 × 4 parallel processing units. Cellular nonlinear network in this study has 16, 384 nodes arranged in 128 × 128 normal grid form. The evolution algorithm of the network is executed by the hardware implemented on a Xilinx XC2VP30-FF896 FPGA chip using fixed-point arithmetic. The FPGA-based platform has an on-line monitor output in order to observe active wave evolution and a host computer in order to program the network. Using fixed-point number format rather than floating-point number format has some advantages in the sense of speed and resource usage. The implementation in this study can be adapted to observe Doppler Effect on traveling waves and autowaves.}},
keywords = {{Cellular Neural/Nonlinear Networks (CNNs), Wave Computer, Field Programmable Gate Array (FPGA), Fixed-Point Arithmetic.}},
doi = {https://doi.org/10.1109/ISCAS.2015.7168933}}
author = {Karakaya, Baris and Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{Wave Computer Core Using Fixed-point Arithmetic}},
booktitle = {{2015 IEEE International Symposium on Circuits and Systems (ISCAS)}},
year = {2015},
month = {May},
pages = {1514-1517},
abstract = {{In this paper, success on cellular nonlinear network emulator core that generates active waves such as autowaves and traveling waves is intended. This wave computer core has 4 × 4 parallel processing units. Cellular nonlinear network in this study has 16, 384 nodes arranged in 128 × 128 normal grid form. The evolution algorithm of the network is executed by the hardware implemented on a Xilinx XC2VP30-FF896 FPGA chip using fixed-point arithmetic. The FPGA-based platform has an on-line monitor output in order to observe active wave evolution and a host computer in order to program the network. Using fixed-point number format rather than floating-point number format has some advantages in the sense of speed and resource usage. The implementation in this study can be adapted to observe Doppler Effect on traveling waves and autowaves.}},
keywords = {{Cellular Neural/Nonlinear Networks (CNNs), Wave Computer, Field Programmable Gate Array (FPGA), Fixed-Point Arithmetic.}},
doi = {https://doi.org/10.1109/ISCAS.2015.7168933}}
[M11]
Yeniçeri, R., Abtioğlu, E., Gövem, B., Yalçın, M.E.,
"A 16 × 16 Cellular Logical Network with Partial Reconfiguration Feature,"
Proc. of 14th Cellular Nanoscale Networks and their Applications (CNNA 2014),
Notre Dame, IN, USA, Jul 29–31, 2014.
@inproceedings{yenicerirM11,
author = {Yeniceri, Ramazan and Abtioglu, Emerah and Govem, Burak and Yalcin, Mustak Erhan},
title = {{A 16 $\times$ 16 Cellular Logical Network with Partial Reconfiguration Feature}},
booktitle = {{2014 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA)}},
year = {2014},
month = {July},
pages = {1-2},
abstract = {{Partial Reconfiguration (PR) has been providing a new lever in digital designs since that feature emerged with practical tools. Similar to changing the program running on a microprocessor, partial reconfiguration is changing the hardware configured on a Field Programmable Gate Array in run-time. In this paper, a Cellular Logical Network performing Boolean functions in order to execute trigger-wave evolution is proposed. The network is endowed with PR feature, thus the functions of the cells are changed by reconfiguring them. That relieves us of the complex cell design in which all possible functions are embedded.}},
doi = {https://doi.org/10.1109/CNNA.2014.6888620}}
author = {Yeniceri, Ramazan and Abtioglu, Emerah and Govem, Burak and Yalcin, Mustak Erhan},
title = {{A 16 $\times$ 16 Cellular Logical Network with Partial Reconfiguration Feature}},
booktitle = {{2014 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA)}},
year = {2014},
month = {July},
pages = {1-2},
abstract = {{Partial Reconfiguration (PR) has been providing a new lever in digital designs since that feature emerged with practical tools. Similar to changing the program running on a microprocessor, partial reconfiguration is changing the hardware configured on a Field Programmable Gate Array in run-time. In this paper, a Cellular Logical Network performing Boolean functions in order to execute trigger-wave evolution is proposed. The network is endowed with PR feature, thus the functions of the cells are changed by reconfiguring them. That relieves us of the complex cell design in which all possible functions are embedded.}},
doi = {https://doi.org/10.1109/CNNA.2014.6888620}}
[M10]
Yeniçeri, R., Yalçın, M.E.,
"The Doppler Effect with Input Driven Autowaves,"
Proc. of 21st European Conference on Circuit Theory and Design (ECCTD 2013),
Dresden, Germany, Sep 8–12, 2013.
@inproceedings{yenicerirM10,
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{The Doppler Effect with Input Driven Autowaves}},
booktitle = {{2013 European Conference on Circuit Theory and Design (ECCTD)}},
year = {2013},
month = {September},
pages = {1-4},
abstract = {{The autowave, which is a kind of nonlinear wave, is easy to generate but difficult to control its source on networks. This paper proposes a new configuration of a Cellular Nonlinear Network and special constant valued input patterns in order to generate autowaves and control its source. It is also shown in this paper that the Doppler Effect is still observed on autowaves with moving source. In this paper, the input pattern is moved continuously to keep the continuity of the autowave evolution. Autowaves can solve the path planning problem with known techniques. Furthermore, the Doppler Effect provides a feature about source's motion. Controlling the autowave source using only the inputs of the network is the novelty of this paper which increases the precision of tracking the source motion in CNN based path planning algorithms.}},
keywords = {},
doi = {https://doi.org/10.1109/ECCTD.2013.6662235}}
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{The Doppler Effect with Input Driven Autowaves}},
booktitle = {{2013 European Conference on Circuit Theory and Design (ECCTD)}},
year = {2013},
month = {September},
pages = {1-4},
abstract = {{The autowave, which is a kind of nonlinear wave, is easy to generate but difficult to control its source on networks. This paper proposes a new configuration of a Cellular Nonlinear Network and special constant valued input patterns in order to generate autowaves and control its source. It is also shown in this paper that the Doppler Effect is still observed on autowaves with moving source. In this paper, the input pattern is moved continuously to keep the continuity of the autowave evolution. Autowaves can solve the path planning problem with known techniques. Furthermore, the Doppler Effect provides a feature about source's motion. Controlling the autowave source using only the inputs of the network is the novelty of this paper which increases the precision of tracking the source motion in CNN based path planning algorithms.}},
keywords = {},
doi = {https://doi.org/10.1109/ECCTD.2013.6662235}}
[M9]
Yeniçeri, R., Ustaoğlu, B., Yalçın, M.E.,
"Throughput Enhancement for a New Time-delay Sampled-data System Based True Random Bit Generator,"
Proc. of 21st European Conference on Circuit Theory and Design (ECCTD 2013),
Dresden, Germany, Sep 8–12, 2013.
@inproceedings{yenicerirM9,
author = {Yeniceri, Ramazan and Ustaoglu, Buse and Yalcin, Mustak Erhan},
title = {{Throughput Enhancement for a New Time-delay Sampled-data System Based True Random Bit Generator}},
booktitle = {{2013 European Conference on Circuit Theory and Design (ECCTD)}},
year = {2013},
month = {September},
pages = {1-4},
abstract = {{In this paper, a throughput enhanced version of a new True Random Bit Generator (TRBG) based on a time-delay sampled-data system is proposed. This new TRBG has both analog and digital parts, which provides the dynamic behavior and the sample and delay process, respectively. The simple system equations and the ease of implementation make this new TRBG very practical. The only required components for the implementation of the proposed system are commonly used Op Amps, resistors and capacitors with a chain of D-type flip-flops. The main contribution of this paper is the increase in random bit generation rate provided by two identical but unsynchronized cooperating circuits compared to the single circuit setup. As experienced, a 2.5 times greater random bit generation rate is achieved by this approach. In order to measure the statistical performance, the contemporary NIST 800-22rev1a Statistical Test Suite is used and it is experienced that the throughput enhancement is achieved with pass results from all these statistical tests.}},
doi = {https://doi.org/10.1109/ECCTD.2013.6662263}}
author = {Yeniceri, Ramazan and Ustaoglu, Buse and Yalcin, Mustak Erhan},
title = {{Throughput Enhancement for a New Time-delay Sampled-data System Based True Random Bit Generator}},
booktitle = {{2013 European Conference on Circuit Theory and Design (ECCTD)}},
year = {2013},
month = {September},
pages = {1-4},
abstract = {{In this paper, a throughput enhanced version of a new True Random Bit Generator (TRBG) based on a time-delay sampled-data system is proposed. This new TRBG has both analog and digital parts, which provides the dynamic behavior and the sample and delay process, respectively. The simple system equations and the ease of implementation make this new TRBG very practical. The only required components for the implementation of the proposed system are commonly used Op Amps, resistors and capacitors with a chain of D-type flip-flops. The main contribution of this paper is the increase in random bit generation rate provided by two identical but unsynchronized cooperating circuits compared to the single circuit setup. As experienced, a 2.5 times greater random bit generation rate is achieved by this approach. In order to measure the statistical performance, the contemporary NIST 800-22rev1a Statistical Test Suite is used and it is experienced that the throughput enhancement is achieved with pass results from all these statistical tests.}},
doi = {https://doi.org/10.1109/ECCTD.2013.6662263}}
[M8]
Yeniçeri, R., Yalçın, M.E.,
"A New CNN Based Path Planning Algorithm Improved by the Doppler Effect,"
Proc. of 13th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2012),
Turin, Italy, Aug 29–31, 2012.
@inproceedings{yenicerirM8,
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{A New CNN Based Path Planning Algorithm Improved by the Doppler Effect}},
booktitle = {{2012 13th International Workshop on Cellular Nanoscale Networks and their Applications}},
year = {2012},
month = {August},
pages = {1-5},
abstract = {{Many path planning and navigation papers using Cellular Neural/Nonlinear Networks (CNN) are found in literature. High proportion of these works originated by wave processing feature of CNN. This paper proposes a special condition of a known Cellular Nonlinear Network model which makes the network very proper to obtain nested and repetitive travelling waves. The Doppler effect appears as a corollary using this special condition. The main contribution of the Doppler effect to the path planning applications that uses CNNs is giving an opportunity to adjust the tracker's speed or change the route completely, dependent to the target's motion. By this way, this paper gains a new qualification to the CNN-based wave computing techniques putting the wave source's motion into use.}},
doi = {https://doi.org/10.1109/CNNA.2012.6331428}}
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{A New CNN Based Path Planning Algorithm Improved by the Doppler Effect}},
booktitle = {{2012 13th International Workshop on Cellular Nanoscale Networks and their Applications}},
year = {2012},
month = {August},
pages = {1-5},
abstract = {{Many path planning and navigation papers using Cellular Neural/Nonlinear Networks (CNN) are found in literature. High proportion of these works originated by wave processing feature of CNN. This paper proposes a special condition of a known Cellular Nonlinear Network model which makes the network very proper to obtain nested and repetitive travelling waves. The Doppler effect appears as a corollary using this special condition. The main contribution of the Doppler effect to the path planning applications that uses CNNs is giving an opportunity to adjust the tracker's speed or change the route completely, dependent to the target's motion. By this way, this paper gains a new qualification to the CNN-based wave computing techniques putting the wave source's motion into use.}},
doi = {https://doi.org/10.1109/CNNA.2012.6331428}}
[M7]
Tükel, M., Yeniçeri, R., Yalçın, M.E.,
"Nonlinear Spatio-temporal Wave Computing for Real-time Applications on GPU,"
Proc. of 13th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2012),
Turin, Italy, Aug 29–31, 2012.
@inproceedings{yenicerirM7,
author = {Tukel, Mehmet and Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{Nonlinear Spatio-temporal Wave Computing for Real-time Applications on GPU}},
booktitle = {{2012 13th International Workshop on Cellular Nanoscale Networks and their Applications}},
year = {2012},
month = {August},
pages = {1-5},
abstract = {{In this work, active wave simulation on Cellular Nonlinear Network was computed for path planning on the GPU of a NVIDIA GTX275 video card. In software part, QtOpenCL, which is a wrapper library of OpenCL, was used to make code portable for systems with different GPUs. We achieved promising results comparing to results achieved by both CPU and FPGA. We have implemented different hardware and software solutions to path planning problem for 2-D media in real-time. They were almost at limit of real-time requirements because of some bottlenecks such as low communication bandwidth and low resolution of network. In this work, by utilizing GPUs, we performed 60000 iterations per second for simulation of 128×128 node network while we achieved at most 35 iterations per second with software on an Intel Core 2 Duo P8700 processor. We also achieved 36 iterations per second for 3-D active wave simulation of a 256 × 256 × 256 network on GPU.}},
doi = {https://doi.org/10.1109/CNNA.2012.6331419}}
author = {Tukel, Mehmet and Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{Nonlinear Spatio-temporal Wave Computing for Real-time Applications on GPU}},
booktitle = {{2012 13th International Workshop on Cellular Nanoscale Networks and their Applications}},
year = {2012},
month = {August},
pages = {1-5},
abstract = {{In this work, active wave simulation on Cellular Nonlinear Network was computed for path planning on the GPU of a NVIDIA GTX275 video card. In software part, QtOpenCL, which is a wrapper library of OpenCL, was used to make code portable for systems with different GPUs. We achieved promising results comparing to results achieved by both CPU and FPGA. We have implemented different hardware and software solutions to path planning problem for 2-D media in real-time. They were almost at limit of real-time requirements because of some bottlenecks such as low communication bandwidth and low resolution of network. In this work, by utilizing GPUs, we performed 60000 iterations per second for simulation of 128×128 node network while we achieved at most 35 iterations per second with software on an Intel Core 2 Duo P8700 processor. We also achieved 36 iterations per second for 3-D active wave simulation of a 256 × 256 × 256 network on GPU.}},
doi = {https://doi.org/10.1109/CNNA.2012.6331419}}
[M6]
Ayhan, T., Yeniçeri, R., Ergünay, S., Yalçın, M.E.,
"Hybrid Processor Population for Odor Processing,"
2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012),
pp. 177-180, Seoul, Korea, May 20–23, 2012.
@inproceedings{yenicerirM6,
author = {Ayhan, Tuba and Yeniceri, Ramazan and Ergunay, Selman and Yalcin, Mustak Erhan},
title = {{Hybrid Processor Population for Odor Processing}},
booktitle = {{2012 IEEE International Symposium on Circuits and Systems (ISCAS)}},
year = {2012},
month = {May},
pages = {177-180},
abstract = {{Some computationally complex problems require complex solutions in terms of number of processors and diversity of computation methods. Metabolic systems are naturally capable of solving complex problems; they are mathematically modelled with hundreds of differential equations. In order to understand those metabolisms or simply replicate their functions in engineering problems, we need a large network of processors that is designed to mimic biological systems. Moreover, many processes take place in metabolic networks are results of collaboration of different types of cells that are randomly located. Therefore, bio-inspired topologically random mega-core networks of hybrid processors are needed to solve complex biological problems. Introducing randomness into a hybrid processor network that employs thousands of processors requires special techniques. We are proposing a solution to mega-core architectures with multi-type processors. Our aim in this work is to obtain a very large collaborative network of hybrid processors that has reconfigurable random topology. Our solution provides reconfiguration of a large network with different types of processors so that the network can be adapted to many different problems or can be used to mimic different metabolic functions. In this work, we are trying to solve the speed problem in artificial olfaction systems by a hybrid processor feature extractor that performs spatio-temporal coding inspired from nature. The technique is also efficient in realization; it is based on adding an 'identity' pin that will be used to reconfigure the identical processors. In this work we propose our technique to generate hybrid processor populations on any array platform or networks of single type processors and report the implementation on FPGA.}},
doi = {https://doi.org/10.1109/ISCAS.2012.6271607}}
author = {Ayhan, Tuba and Yeniceri, Ramazan and Ergunay, Selman and Yalcin, Mustak Erhan},
title = {{Hybrid Processor Population for Odor Processing}},
booktitle = {{2012 IEEE International Symposium on Circuits and Systems (ISCAS)}},
year = {2012},
month = {May},
pages = {177-180},
abstract = {{Some computationally complex problems require complex solutions in terms of number of processors and diversity of computation methods. Metabolic systems are naturally capable of solving complex problems; they are mathematically modelled with hundreds of differential equations. In order to understand those metabolisms or simply replicate their functions in engineering problems, we need a large network of processors that is designed to mimic biological systems. Moreover, many processes take place in metabolic networks are results of collaboration of different types of cells that are randomly located. Therefore, bio-inspired topologically random mega-core networks of hybrid processors are needed to solve complex biological problems. Introducing randomness into a hybrid processor network that employs thousands of processors requires special techniques. We are proposing a solution to mega-core architectures with multi-type processors. Our aim in this work is to obtain a very large collaborative network of hybrid processors that has reconfigurable random topology. Our solution provides reconfiguration of a large network with different types of processors so that the network can be adapted to many different problems or can be used to mimic different metabolic functions. In this work, we are trying to solve the speed problem in artificial olfaction systems by a hybrid processor feature extractor that performs spatio-temporal coding inspired from nature. The technique is also efficient in realization; it is based on adding an 'identity' pin that will be used to reconfigure the identical processors. In this work we propose our technique to generate hybrid processor populations on any array platform or networks of single type processors and report the implementation on FPGA.}},
doi = {https://doi.org/10.1109/ISCAS.2012.6271607}}
[M5]
Ergünay, S., Yeniçeri, R., Yalçın, M.E.,
"Hardware-Software Co-design of Nonlinear Active Wave Generator with Microblaze Soft Core Processor,"
Proc. of 2010 International Symposium on Nonlinear Theory and its Applications (NOLTA2010),
pp. 157-160, Krakow, Poland, Sept. 5–8, 2010.
@inproceedings{yenicerirM5,
author = {Ergunay, Selman and Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{Hardware-Software Co-design of Nonlinear Active Wave Generator with Microblaze Soft Core Processor}},
booktitle = {{2010 International Symposium on Nonlinear Theory and its Applications (NOLTA2010)}},
year = {2010},
month = {September},
pages = {157-160},
abstract = {{This paper introduces a hardware-software co-design of a Cellular Nonlinear Network (CNN) emulator. The Cellular Nonlinear Network is an two- dimensional array of locally coupled Nonlinear Processing Elements (NPEs). The network is used to observe evolution of spatio-temporal waves such as autowaves, travelling waves and spiral waves. The software part of the design controls the custom NPEs which are the hardware part of the design. In order to reach high performance, the software part provides control exibility on hardware part which is vital for developing and executing active wave based computing algorithms. The system has been implemented on Xilinx Spartan 3E1600E FPGA with Microblaze soft core processor using Embedded Development Kit (EDK) design tools.}},
doi = {https://doi.org/10.34385/proc.44.A3L-B3}}
author = {Ergunay, Selman and Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{Hardware-Software Co-design of Nonlinear Active Wave Generator with Microblaze Soft Core Processor}},
booktitle = {{2010 International Symposium on Nonlinear Theory and its Applications (NOLTA2010)}},
year = {2010},
month = {September},
pages = {157-160},
abstract = {{This paper introduces a hardware-software co-design of a Cellular Nonlinear Network (CNN) emulator. The Cellular Nonlinear Network is an two- dimensional array of locally coupled Nonlinear Processing Elements (NPEs). The network is used to observe evolution of spatio-temporal waves such as autowaves, travelling waves and spiral waves. The software part of the design controls the custom NPEs which are the hardware part of the design. In order to reach high performance, the software part provides control exibility on hardware part which is vital for developing and executing active wave based computing algorithms. The system has been implemented on Xilinx Spartan 3E1600E FPGA with Microblaze soft core processor using Embedded Development Kit (EDK) design tools.}},
doi = {https://doi.org/10.34385/proc.44.A3L-B3}}
[M4]
Kılıç, V., Yeniçeri, R., Yalçın, M.E.,
“A New Active Wave Computing Based Real Time Mobile Robot Navigation Algorithm for Dynamic Environment,"
Proc. of 12th International Workshop on Cellular Nanoscale Networks and Applications (CNNA 2010),
pp. 1-6, Berkeley, CA, USA, February 3-5, 2010.
@inproceedings{yenicerirM4,
author = {Kilic, Volkan and Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{A New Active Wave Computing Based Real Time Mobile Robot Navigation Algorithm for Dynamic Environment}},
booktitle = {{2010 12th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2010)}},
year = {2010},
month = {February},
pages = {1-6},
abstract = {{This paper introduces an active wave computing based algorithm for real-time robot navigation problem in dynamically changing environment and presents a real test setup with a roving robot. Travelling waves propagated on Cellular Neural Network (CNN) were employed by the system to find the shortest path as proposed in our previous work. The setup has a ceiling camera which captures an image of the top view of the platform at almost every one second. After preprocessing of this image, it is loaded to the network and an active wave which is generated by this network is propagated until the robot is covered by the wave. This method reduces the simulation time and speeds up the system. Although the robot is navigated in a dynamically changing environment, the system does not need to check the moving obstacles. The algorithm proposed here always generates a solution for the current state of the platform without the information about its past states. At every repetition of the algorithm, the target position is updated by the system if it is changed. Any change of the target position is immediately applied to the location of the wave source. Hence the system becomes working in dynamic environment with dynamic target.}},
keywords = {{CNNs, Cellular Wave Computing, Path Planning, Real-time Robot Navigation}},
doi = {https://doi.org/10.1109/CNNA.2010.5430279}}
author = {Kilic, Volkan and Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{A New Active Wave Computing Based Real Time Mobile Robot Navigation Algorithm for Dynamic Environment}},
booktitle = {{2010 12th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2010)}},
year = {2010},
month = {February},
pages = {1-6},
abstract = {{This paper introduces an active wave computing based algorithm for real-time robot navigation problem in dynamically changing environment and presents a real test setup with a roving robot. Travelling waves propagated on Cellular Neural Network (CNN) were employed by the system to find the shortest path as proposed in our previous work. The setup has a ceiling camera which captures an image of the top view of the platform at almost every one second. After preprocessing of this image, it is loaded to the network and an active wave which is generated by this network is propagated until the robot is covered by the wave. This method reduces the simulation time and speeds up the system. Although the robot is navigated in a dynamically changing environment, the system does not need to check the moving obstacles. The algorithm proposed here always generates a solution for the current state of the platform without the information about its past states. At every repetition of the algorithm, the target position is updated by the system if it is changed. Any change of the target position is immediately applied to the location of the wave source. Hence the system becomes working in dynamic environment with dynamic target.}},
keywords = {{CNNs, Cellular Wave Computing, Path Planning, Real-time Robot Navigation}},
doi = {https://doi.org/10.1109/CNNA.2010.5430279}}
[M3]
Yeniçeri, R., Yalçın, M.E.,
“An Emulated Digital Wave Computer Core Implementation,"
Proc. of European Conference on Circuit Theory and Design 2009 (ECCTD'09),
pp. 831-834, Antalya, Turkey, August 23-27, 2009.
@inproceedings{yenicerirM3,
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{An Emulated Digital Wave Computer Core Implementation}},
booktitle = {{2009 European Conference on Circuit Theory and Design}},
year = {2009},
month = {August},
pages = {831-834},
abstract = {{In this paper, a novel cellular nonlinear network emulator core which executes wave computing within an FPGA-based platform is proposed. This wave computer core has 4 × 4 parallel processing units and emulates 16, 384 nodes which are arranged in 128 × 128 normal grid form. The wave computer core can be programmed to generate active waves such as autowaves, travelling waves and spiral waves, and also allow to have an inhomogeneous network using fixed-state options. By virtue of its on chip memory and floating point number arithmetics ability, high emulation speed and high precision on variable values are achieved. The FPGA wave computer has not only an online monitor output to observe active wave evaluation, also a communication interface which allows to program the network with host computer. The introduced system was experimented in a path planning application and can be used to develop more active wave computing based algorithms for image processing and path planning.}},
keywords = {{Cellular Neural/Nonlinear Networks (CNNs), Wave Computer, Core Design, Field-Programmable Gate Array (FPGA)}},
doi = {https://doi.org/10.1109/ECCTD.2009.5275112}}
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{An Emulated Digital Wave Computer Core Implementation}},
booktitle = {{2009 European Conference on Circuit Theory and Design}},
year = {2009},
month = {August},
pages = {831-834},
abstract = {{In this paper, a novel cellular nonlinear network emulator core which executes wave computing within an FPGA-based platform is proposed. This wave computer core has 4 × 4 parallel processing units and emulates 16, 384 nodes which are arranged in 128 × 128 normal grid form. The wave computer core can be programmed to generate active waves such as autowaves, travelling waves and spiral waves, and also allow to have an inhomogeneous network using fixed-state options. By virtue of its on chip memory and floating point number arithmetics ability, high emulation speed and high precision on variable values are achieved. The FPGA wave computer has not only an online monitor output to observe active wave evaluation, also a communication interface which allows to program the network with host computer. The introduced system was experimented in a path planning application and can be used to develop more active wave computing based algorithms for image processing and path planning.}},
keywords = {{Cellular Neural/Nonlinear Networks (CNNs), Wave Computer, Core Design, Field-Programmable Gate Array (FPGA)}},
doi = {https://doi.org/10.1109/ECCTD.2009.5275112}}
[M2]
Yeniçeri, R., Yalçın, M.E.,
"Path Planning on Cellular Nonlinear Network Using Active Wave Computing Technique,"
Bioengineered and Bioinspired Systems IV, Proc. SPIE,
Vol. 7365, Dresden, Germany, May 3-5, 2009.
[T4] Gönen, B., Yeniçeri, R., Ayhan, T., Yalçın, M.E., "FPGA Üzerinde İzgesel Bastırma Yöntemi ile Konuşma İşaretinden Gürültü Giderme," IEEE 19. Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU 2011) Bildiri Kitabı, sayfa 598-601, Antalya, 20-22 Nisan 2011.
@inproceedings{yenicerirM2,
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{Path Planning on Cellular Nonlinear Network Using Active Wave Computing Technique}},
booktitle = {{Bioengineered and Bioinspired Systems IV}},
volume = {7365},
publisher = {{SPIE}},
organization = {{International Society for Optics and Photonics}},
year = {2009},
month = {May},
pages = {736508},
abstract = {{This paper introduces a simple algorithm to solve robot path finding problem using active wave computing techniques. A two-dimensional Cellular Neural/Nonlinear Network (CNN), consist of relaxation oscillators, has been used to generate active waves and to process the visual information. The network, which has been implemented on a Field Programmable Gate Array (FPGA) chip, has the feature of being programmed, controlled and observed by a host computer. The arena of the robot is modelled as the medium of the active waves on the network. Active waves are employed to cover the whole medium with their own dynamics, by starting from an initial point. The proposed algorithm is achieved by observing the motion of the wave-front of the active waves. Host program first loads the arena model onto the active wave generator network and command to start the generation. Then periodically pulls the network image from the generator hardware to analyze evolution of the active waves. When the algorithm is completed, vectorial data image is generated. The path from any of the pixel on this image to the active wave generating pixel is drawn by the vectors on this image. The robot arena may be a complicated labyrinth or may have a simple geometry. But, the arena surface always must be flat. Our Autowave Generator CNN implementation which is settled on the Xilinx University Program Virtex-II Pro Development System is operated by a MATLAB program running on the host computer. As the active wave generator hardware has 16, 384 neurons, an arena with 128 × 128 pixels can be modeled and solved by the algorithm. The system also has a monitor and network image is depicted on the monitor simultaneously.}},
keywords = {{CNNs, cellular wave computing, active waves, path finding, robot navigation, Field-Programmable Gate Array (FPGA)}},
doi = {https://doi.org/10.1117/12.821669}}
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{Path Planning on Cellular Nonlinear Network Using Active Wave Computing Technique}},
booktitle = {{Bioengineered and Bioinspired Systems IV}},
volume = {7365},
publisher = {{SPIE}},
organization = {{International Society for Optics and Photonics}},
year = {2009},
month = {May},
pages = {736508},
abstract = {{This paper introduces a simple algorithm to solve robot path finding problem using active wave computing techniques. A two-dimensional Cellular Neural/Nonlinear Network (CNN), consist of relaxation oscillators, has been used to generate active waves and to process the visual information. The network, which has been implemented on a Field Programmable Gate Array (FPGA) chip, has the feature of being programmed, controlled and observed by a host computer. The arena of the robot is modelled as the medium of the active waves on the network. Active waves are employed to cover the whole medium with their own dynamics, by starting from an initial point. The proposed algorithm is achieved by observing the motion of the wave-front of the active waves. Host program first loads the arena model onto the active wave generator network and command to start the generation. Then periodically pulls the network image from the generator hardware to analyze evolution of the active waves. When the algorithm is completed, vectorial data image is generated. The path from any of the pixel on this image to the active wave generating pixel is drawn by the vectors on this image. The robot arena may be a complicated labyrinth or may have a simple geometry. But, the arena surface always must be flat. Our Autowave Generator CNN implementation which is settled on the Xilinx University Program Virtex-II Pro Development System is operated by a MATLAB program running on the host computer. As the active wave generator hardware has 16, 384 neurons, an arena with 128 × 128 pixels can be modeled and solved by the algorithm. The system also has a monitor and network image is depicted on the monitor simultaneously.}},
keywords = {{CNNs, cellular wave computing, active waves, path finding, robot navigation, Field-Programmable Gate Array (FPGA)}},
doi = {https://doi.org/10.1117/12.821669}}
[M1]
Yeniçeri, R., Yalçın, M.E.,
"An Implementation of 2D Locally Coupled Relaxation Oscillators on an FPGA for Real-time Autowave Generation,"
Proc. of 11th International Workshop on Cellular Neural Networks and their Applications (CNNA 2008),
pp. 29-33, Santiago de Compostela, Spain, July 14-16, 2008.
@inproceedings{yenicerirM1,
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{An Implementation of 2D Locally Coupled Relaxation Oscillators on an FPGA for Real-time Autowave Generation}},
booktitle = {{2008 11th International Workshop on Cellular Neural Networks and Their Applications}},
year = {2008},
month = {July},
pages = {29-33},
abstract = {{This paper introduces a digital implementation of a new simple programmable autowave generator network on a Field Programmable Gate Array (FPGA). The network is a two dimensional reaction-diffusion Cellular Neural Network which consists of relaxation oscillators. The introduced implementation successfully simulates 25,600 neurons in real-time with novel Cellular Neural Processing Network architecture which uses floatingpoint number format. The implementation allows simulating the network with high numeric resolution and real-time monitoring of the evolution of autowaves. This FPGA implementation of the network provides a suitable platform to explore spatiotemporal behavior and to implement wave computing algorithms.}},
keywords = {{CNNs, Cellular Wave Computing, Field Programmable Gate Array, Autowaves, Relaxation oscillators}},
doi = {https://doi.org/10.1109/CNNA.2008.4588645}}
author = {Yeniceri, Ramazan and Yalcin, Mustak Erhan},
title = {{An Implementation of 2D Locally Coupled Relaxation Oscillators on an FPGA for Real-time Autowave Generation}},
booktitle = {{2008 11th International Workshop on Cellular Neural Networks and Their Applications}},
year = {2008},
month = {July},
pages = {29-33},
abstract = {{This paper introduces a digital implementation of a new simple programmable autowave generator network on a Field Programmable Gate Array (FPGA). The network is a two dimensional reaction-diffusion Cellular Neural Network which consists of relaxation oscillators. The introduced implementation successfully simulates 25,600 neurons in real-time with novel Cellular Neural Processing Network architecture which uses floatingpoint number format. The implementation allows simulating the network with high numeric resolution and real-time monitoring of the evolution of autowaves. This FPGA implementation of the network provides a suitable platform to explore spatiotemporal behavior and to implement wave computing algorithms.}},
keywords = {{CNNs, Cellular Wave Computing, Field Programmable Gate Array, Autowaves, Relaxation oscillators}},
doi = {https://doi.org/10.1109/CNNA.2008.4588645}}
Conference Papers in Turkish
[T15]
Küçükoğlu, A.G., Yeniçeri, R.,
"K Bant Frekans Modülasyonlu Sürekli Dalga Radarı Tasarımı ve Gerçeklenmesi,"
4th International Eurasian Conference on Science, Engineering and Technology (EurasianSciEnTech 2022),
Ankara, 14-16 Aralık 2022.
@inproceedings{yenicerirT15,
author = {Küçükoğlu, Abdulkadir Geylani and Yeniçeri, Ramazan},
title = {{K Bant Frekans Modülasyonlu Sürekli Dalga Radarı Tasarımı ve Gerçeklenmesi}},
booktitle = {{4th International Eurasian Conference on Science, Engineering and Technology (EurasianSciEnTech 2022)}},
year = {2022},
month = {December},
pages = {1110-1117},
abstract = {{Bu çalışmada K bant frekans modülasyonlu sürekli dalga (FMSD) radarı detaylı olarak analiz edilerek modellenmekte ve gerçeklenmektedir. RF ön uç benzetimleri için AWR Microwave Office programı Visual System Simulation (VSS) benzetim aracı kullanılmaktadır. Bu program ile faz kilitli döngü (ing. Phase Lock Loop), voltaj kontrollü osilatör (ing. Voltage Controlled Oscillator) blokları; güç yükseltici ve düşük gürültülü yükselteçi; alçak geçiren ve bant geçiren filtreleri; verici ve alıcı antenleri; iletim kanalı; mikser; temel bant filtre ve ayarlanabilir kazanç yükselteç; analog sayısal dönüştürücü (ing. ADC) ve hızlı Fourier dönüşüm (ing. FFT) modellenmektedir. K bantta tasarlanan donanımda temel FMSD radar blokları; voltaj kontrollü osilatör içeren mikser entegresi baz alınarak, alçak geçiren ve bant geçiren filtreler, anten, güç bölücü, analog filtre ve yükselteçler tasarlanmaktadır. C bantta faz kilitli döngü, düşük gürültülü yükselteç, mikser, güç bölücü, ayarlanabilir kazanç kontrollü yükselteç geliştirme kartları ve anten kullanılarak; alçak geçiren ve bant geçiren filtreler tasarlanarak FMSD radar sistemi oluşturulmaktadır. Kurulan sistem kullanılarak FMSD radarın tarama periyodu, faz gürültüsü, harmonik şiddeti, jammer, doppler etkisi parametrelerinin radar performansına etkileri incelenmektedir. FPGA ve ADC kullanılarak radar sinyal işleme algoritmasının geliştirilmesi için test verileri toplanmaktadır. Toplanan veriler MATLAB ortamında işlenerek mesafe ve hız hesaplamaları yapılmaktadır. Radar sinyal işleme algoritması sınırlı vuru yanıtı (ing. FIR) bant geçiren filtre, pencereleme, FFT, sabit yanlış alarm oranı (ing. CFAR) detektörü, hareketli ortalama (ing. moving average) mesafe ve hız hesaplama algoritmalarını içermektedir.}},
keywords = {{FMSD radar, mesafe ölçümü, sistem benzetimi}}}
author = {Küçükoğlu, Abdulkadir Geylani and Yeniçeri, Ramazan},
title = {{K Bant Frekans Modülasyonlu Sürekli Dalga Radarı Tasarımı ve Gerçeklenmesi}},
booktitle = {{4th International Eurasian Conference on Science, Engineering and Technology (EurasianSciEnTech 2022)}},
year = {2022},
month = {December},
pages = {1110-1117},
abstract = {{Bu çalışmada K bant frekans modülasyonlu sürekli dalga (FMSD) radarı detaylı olarak analiz edilerek modellenmekte ve gerçeklenmektedir. RF ön uç benzetimleri için AWR Microwave Office programı Visual System Simulation (VSS) benzetim aracı kullanılmaktadır. Bu program ile faz kilitli döngü (ing. Phase Lock Loop), voltaj kontrollü osilatör (ing. Voltage Controlled Oscillator) blokları; güç yükseltici ve düşük gürültülü yükselteçi; alçak geçiren ve bant geçiren filtreleri; verici ve alıcı antenleri; iletim kanalı; mikser; temel bant filtre ve ayarlanabilir kazanç yükselteç; analog sayısal dönüştürücü (ing. ADC) ve hızlı Fourier dönüşüm (ing. FFT) modellenmektedir. K bantta tasarlanan donanımda temel FMSD radar blokları; voltaj kontrollü osilatör içeren mikser entegresi baz alınarak, alçak geçiren ve bant geçiren filtreler, anten, güç bölücü, analog filtre ve yükselteçler tasarlanmaktadır. C bantta faz kilitli döngü, düşük gürültülü yükselteç, mikser, güç bölücü, ayarlanabilir kazanç kontrollü yükselteç geliştirme kartları ve anten kullanılarak; alçak geçiren ve bant geçiren filtreler tasarlanarak FMSD radar sistemi oluşturulmaktadır. Kurulan sistem kullanılarak FMSD radarın tarama periyodu, faz gürültüsü, harmonik şiddeti, jammer, doppler etkisi parametrelerinin radar performansına etkileri incelenmektedir. FPGA ve ADC kullanılarak radar sinyal işleme algoritmasının geliştirilmesi için test verileri toplanmaktadır. Toplanan veriler MATLAB ortamında işlenerek mesafe ve hız hesaplamaları yapılmaktadır. Radar sinyal işleme algoritması sınırlı vuru yanıtı (ing. FIR) bant geçiren filtre, pencereleme, FFT, sabit yanlış alarm oranı (ing. CFAR) detektörü, hareketli ortalama (ing. moving average) mesafe ve hız hesaplama algoritmalarını içermektedir.}},
keywords = {{FMSD radar, mesafe ölçümü, sistem benzetimi}}}
[T14]
Tanış, M., Bozacı, C., Gezer, S., Yeniçeri, R., Yalçın, M.E.,
"Güç Spektral Yoğunluğu Kullanarak Sahte GPS Sinyali Tespiti,"
10. Savunma Teknolojileri Kongresi (SAVTEK 2022),
Ankara, 13-15 Eylül 2022.
@inproceedings{yenicerirT14,
author = {Tanış, Mustafa and Bozacı, Can and Gezer, Seçkin and Yeniçeri, Ramazan and Yalçın, Müştak Erhan},
title = {{Güç Spektral Yoğunluğu Kullanarak Sahte GPS Sinyali Tespiti}},
booktitle = {{10. Savunma Teknolojileri Kongresi (SAVTEK 2022)}},
year = {2022},
month = {September},
pages = {1347-1355},
abstract = {{Bu çalışmada bir yazılım tabanlı radyo verici (SDR) yardımıyla sahte GPS yayının yapılabildiği ve GPS alıcısının aldatılabildiği deneysel olarak gösterilmiştir. Aldatmaya karşı yüksek frekanslı RF sinyallerini ara frekansa düşürüp örnekleyen bir çevirici yardımıyla elde edinen sinyallerin güç spektral yoğunluğu üzerinden bir yöntem önerilmiş ve gerçekleştirilmiştir. Aldanmayı kısa zamanda fark edebilmek amacıyla çeviriciye bağlı sahada programlanabilir kapı dizilerinden faydalanılmıştır.}},
keywords = {{GPS, Sahte GPS Yayını, Sahte GPS Tespiti, Yazılım Tabanlı Radyo}}}
author = {Tanış, Mustafa and Bozacı, Can and Gezer, Seçkin and Yeniçeri, Ramazan and Yalçın, Müştak Erhan},
title = {{Güç Spektral Yoğunluğu Kullanarak Sahte GPS Sinyali Tespiti}},
booktitle = {{10. Savunma Teknolojileri Kongresi (SAVTEK 2022)}},
year = {2022},
month = {September},
pages = {1347-1355},
abstract = {{Bu çalışmada bir yazılım tabanlı radyo verici (SDR) yardımıyla sahte GPS yayının yapılabildiği ve GPS alıcısının aldatılabildiği deneysel olarak gösterilmiştir. Aldatmaya karşı yüksek frekanslı RF sinyallerini ara frekansa düşürüp örnekleyen bir çevirici yardımıyla elde edinen sinyallerin güç spektral yoğunluğu üzerinden bir yöntem önerilmiş ve gerçekleştirilmiştir. Aldanmayı kısa zamanda fark edebilmek amacıyla çeviriciye bağlı sahada programlanabilir kapı dizilerinden faydalanılmıştır.}},
keywords = {{GPS, Sahte GPS Yayını, Sahte GPS Tespiti, Yazılım Tabanlı Radyo}}}
[T13]
Memiş, S., Yeniçeri, R.,
"6 Serbestlik Derecesine Sahip Bir Sistem Matematik Modelinde Dönüşüm Matrisinin FPGA Üzerinde Donanım Tabanlı Gerçeklenmesi,"
9. Ulusal Havacılık ve Uzay Konferansı (UHUK'2022),
İzmir, 14-16 Eylül 2022.
@inproceedings{yenicerirT13,
author = {Memiş, Sezer and Yeniçeri, Ramazan},
title = {{6 Serbestlik Derecesine Sahip Bir Sistem Matematik Modelinde Dönüşüm Matrisinin FPGA Üzerinde Donanım Tabanlı Gerçeklenmesi}},
booktitle = {{9. Ulusal Havacılık ve Uzay Konferansı (UHUK'2022)}},
year = {2022},
month = {September},
pages = {1-10},
abstract = {{Bu bildiride, 6 serbestlik derecesine sahip bir çok rotorlu matematik modelinin eksen dönüşüm matrisinin FPGA üzerinde donanım tabanlı gerçeklemesi çalışılmıştır. Çalışmada, gerçek zamanlılık ile model temsiliyet seviyesi arasında ödünleşme sorununa sahip yazılım tabanlı gerçeklemeye alternatif olarak donanım tabanlı gerçekleme yöntemi önerilmektedir. Bu yöntem, model doğruluğundan ödün vermeden simülasyon hızını artırırken hava aracı tasarım maliyetlerini azaltmaktadır. Entegrasyon işleminde model güvenilirliğinin ve modülerliğin sağlanabilmesi için model tabanlı tasarım ve otomatik kod üretme yaklaşımları kullanılmıştır. FPGA kaynak kullanımının azaltılması amacıyla standart işlemci mimarisinde tasarlanan bloklarda kaynak paylaşımı yaklaşımı uygulanmıştır.}},
url = {http://uhuk.org.tr/bildiri.php/UHUK-2022-151}}
author = {Memiş, Sezer and Yeniçeri, Ramazan},
title = {{6 Serbestlik Derecesine Sahip Bir Sistem Matematik Modelinde Dönüşüm Matrisinin FPGA Üzerinde Donanım Tabanlı Gerçeklenmesi}},
booktitle = {{9. Ulusal Havacılık ve Uzay Konferansı (UHUK'2022)}},
year = {2022},
month = {September},
pages = {1-10},
abstract = {{Bu bildiride, 6 serbestlik derecesine sahip bir çok rotorlu matematik modelinin eksen dönüşüm matrisinin FPGA üzerinde donanım tabanlı gerçeklemesi çalışılmıştır. Çalışmada, gerçek zamanlılık ile model temsiliyet seviyesi arasında ödünleşme sorununa sahip yazılım tabanlı gerçeklemeye alternatif olarak donanım tabanlı gerçekleme yöntemi önerilmektedir. Bu yöntem, model doğruluğundan ödün vermeden simülasyon hızını artırırken hava aracı tasarım maliyetlerini azaltmaktadır. Entegrasyon işleminde model güvenilirliğinin ve modülerliğin sağlanabilmesi için model tabanlı tasarım ve otomatik kod üretme yaklaşımları kullanılmıştır. FPGA kaynak kullanımının azaltılması amacıyla standart işlemci mimarisinde tasarlanan bloklarda kaynak paylaşımı yaklaşımı uygulanmıştır.}},
url = {http://uhuk.org.tr/bildiri.php/UHUK-2022-151}}
[T12]
Turay, K., Yeniçeri, R.,
"İnsansız Hava Araçları için RTK ve GNSS Uygulamaları,"
9. Ulusal Havacılık ve Uzay Konferansı (UHUK'2022),
İzmir, 14-16 Eylül 2022.
@inproceedings{yenicerirT12,
author = {Turay, Kemal and Yeniçeri, Ramazan},
title = {{İnsansız Hava Araçları için RTK ve GNSS Uygulamaları}},
booktitle = {{9. Ulusal Havacılık ve Uzay Konferansı (UHUK'2022)}},
year = {2022},
month = {September},
pages = {1-27},
abstract = {{Zamanın her aşamasında ihtiyaç duyulan konum bilgisine ulaşmak için insanoğlu, çeşitli çözüm yolları aramıştır. Günümüzde, gelişen teknoloji beraberinde oldukça başarılı bir şekilde, bu sorun, artık bir sorun olmaktan çıkmıştır. Bu sorunun çözümü olarak Global Navigasyon Uydu Sistemleri (Global Navigation Satellite System-GNSS) kullanılmaktadır. GNSS’ler; günümüzde oldukça kapsamlı çalışma alanları olan ve önem arz eden sistemlerdir. Bu çalışmada "İnsansız Hava Araçları İçin RTK ve GNSS Uygulamaları" başlığı altında, ilk olarak; GNSS’lere dair literatür bilgisi, örnekleri ve çalışma prensibine dair bilgiler verilmiştir. Ardından; RTK (Real-Time Kinematics) gibi daha hassas bir konum belirleme sisteminin gelişimi ve çalışma prensibine değinilmiştir. Bu aşamadan sonra, RTK sisteminin performansının incelenmesi amaçlanmış olup insansız hava araçları üzerinde uygulamaları, farklı senaryolarda testleri yapılmıştır. Bu testlerin sonuçları ile sistemin limitleri belirlenmiş ve raporlanmıştır. Ülkemizde bulunan, aynı zamanda kullanıma sunulan TUSAGA Aktif ve dünyada kullanılan TUSAGA benzeri gelişmiş hassas konum belirleme sistemlerinin, insansız hava araçlarındaki uygulamalarına ve limitlerine dair araştırmaların raporlanması ve sonuçların yorumlanması ile çalışma tamamlanmıştır.}},
url = {http://uhuk.org.tr/bildiri.php/UHUK-2022-109}}
author = {Turay, Kemal and Yeniçeri, Ramazan},
title = {{İnsansız Hava Araçları için RTK ve GNSS Uygulamaları}},
booktitle = {{9. Ulusal Havacılık ve Uzay Konferansı (UHUK'2022)}},
year = {2022},
month = {September},
pages = {1-27},
abstract = {{Zamanın her aşamasında ihtiyaç duyulan konum bilgisine ulaşmak için insanoğlu, çeşitli çözüm yolları aramıştır. Günümüzde, gelişen teknoloji beraberinde oldukça başarılı bir şekilde, bu sorun, artık bir sorun olmaktan çıkmıştır. Bu sorunun çözümü olarak Global Navigasyon Uydu Sistemleri (Global Navigation Satellite System-GNSS) kullanılmaktadır. GNSS’ler; günümüzde oldukça kapsamlı çalışma alanları olan ve önem arz eden sistemlerdir. Bu çalışmada "İnsansız Hava Araçları İçin RTK ve GNSS Uygulamaları" başlığı altında, ilk olarak; GNSS’lere dair literatür bilgisi, örnekleri ve çalışma prensibine dair bilgiler verilmiştir. Ardından; RTK (Real-Time Kinematics) gibi daha hassas bir konum belirleme sisteminin gelişimi ve çalışma prensibine değinilmiştir. Bu aşamadan sonra, RTK sisteminin performansının incelenmesi amaçlanmış olup insansız hava araçları üzerinde uygulamaları, farklı senaryolarda testleri yapılmıştır. Bu testlerin sonuçları ile sistemin limitleri belirlenmiş ve raporlanmıştır. Ülkemizde bulunan, aynı zamanda kullanıma sunulan TUSAGA Aktif ve dünyada kullanılan TUSAGA benzeri gelişmiş hassas konum belirleme sistemlerinin, insansız hava araçlarındaki uygulamalarına ve limitlerine dair araştırmaların raporlanması ve sonuçların yorumlanması ile çalışma tamamlanmıştır.}},
url = {http://uhuk.org.tr/bildiri.php/UHUK-2022-109}}
[T11]
Işkın, M.E., Yeniçeri, R.,
"FPGA Tabanlı Görsel Ataletsel Odometri Algoritması için Sensör Sistemi Tasarımı,"
9. Ulusal Havacılık ve Uzay Konferansı (UHUK'2022),
İzmir, 14-16 Eylül 2022.
@inproceedings{yenicerirT11,
author = {Işkın, Mustafa Ensar and Yeniçeri, Ramazan},
title = {{FPGA Tabanlı Görsel Ataletsel Odometri Algoritması için Sensör Sistemi Tasarımı}},
booktitle = {{9. Ulusal Havacılık ve Uzay Konferansı (UHUK'2022)}},
year = {2022},
month = {September},
pages = {1-7},
abstract = {{Otonom araçların sahip olması gereken en önemli bilgilerden birisi kendilerinin konum bilgileridir. Farklı navigasyon teknikleri kullanılarak otonom araçlar konum bilgilerini elde edebilir. Görsel Atalet Odometri (Visual Inertial Odometry), görsel ve atalet verilerini birlikte kullanarak konum tahmini yapabilmektedir. Bu projede Görsel Atalet Odometri algoritması için Zybo Z7-20 SoC kartı kullanılarak gerekli olan görsel ve ivme verilerinin toplanması amaçlanmıştır. Görsel veriyi elde etmek için PCAM 5C adlı kamera modülü kullanılmıştır. İvme verisi ise üzerinde 3 eksen ivmeölçer, 3 eksen gyroscope ve 3 eksen manyetometre bulunan Pmod NAV sensörü kullanılmıştır. İvmeölçer verisini iyileştirmek adına ayrıca gyroscope verisi de kaydedilmiştir. Gyroscope verisini kullanarak ivme verisinden yer çekimi etkisi çıkartılarak daha doğru sonuçlar elde edilebilir. Elde edilen IMU sensör verisi SD karta kaydedilmiş olup, görüntü verisi ise Zybo Z7-20 kartı üzerindek HDMI çıkışından iletilmektedir.}},
url = {http://uhuk.org.tr/bildiri.php/UHUK-2022-107}}
author = {Işkın, Mustafa Ensar and Yeniçeri, Ramazan},
title = {{FPGA Tabanlı Görsel Ataletsel Odometri Algoritması için Sensör Sistemi Tasarımı}},
booktitle = {{9. Ulusal Havacılık ve Uzay Konferansı (UHUK'2022)}},
year = {2022},
month = {September},
pages = {1-7},
abstract = {{Otonom araçların sahip olması gereken en önemli bilgilerden birisi kendilerinin konum bilgileridir. Farklı navigasyon teknikleri kullanılarak otonom araçlar konum bilgilerini elde edebilir. Görsel Atalet Odometri (Visual Inertial Odometry), görsel ve atalet verilerini birlikte kullanarak konum tahmini yapabilmektedir. Bu projede Görsel Atalet Odometri algoritması için Zybo Z7-20 SoC kartı kullanılarak gerekli olan görsel ve ivme verilerinin toplanması amaçlanmıştır. Görsel veriyi elde etmek için PCAM 5C adlı kamera modülü kullanılmıştır. İvme verisi ise üzerinde 3 eksen ivmeölçer, 3 eksen gyroscope ve 3 eksen manyetometre bulunan Pmod NAV sensörü kullanılmıştır. İvmeölçer verisini iyileştirmek adına ayrıca gyroscope verisi de kaydedilmiştir. Gyroscope verisini kullanarak ivme verisinden yer çekimi etkisi çıkartılarak daha doğru sonuçlar elde edilebilir. Elde edilen IMU sensör verisi SD karta kaydedilmiş olup, görüntü verisi ise Zybo Z7-20 kartı üzerindek HDMI çıkışından iletilmektedir.}},
url = {http://uhuk.org.tr/bildiri.php/UHUK-2022-107}}
[T10]
Subaşı, O.C., Köktaş, Y., Karasubaşı, M., Bük, T., Yeniçeri, R.,
"Hava Veri Bilgisayarının Davranış Modellemesi, Donanım Üzerinde Gerçeklenmesi ve SEL Ortamında Kullanımı,"
8. Ulusal Havacılık ve Uzay Konferansı (UHUK'2020),
Ankara, 9-11 Eylül 2020.
@inproceedings{yenicerirT10,
author = {Subaşı, Ozan Can and Köktaş, Y., Karasubaşı, M., Bük, Timuçin and Yeniçeri, Ramazan},
title = {{Hava Veri Bilgisayarının Davranış Modellemesi, Donanım Üzerinde Gerçeklenmesi ve SEL Ortamında Kullanımı}},
booktitle = {{8. Ulusal Havacılık ve Uzay Konferansı (UHUK'2020)}},
year = {2020},
month = {September},
pages = {1-14},
abstract = {{Hava veri bilgisayarı, basınç ve sıcaklık sensörlerinden aldığı ölçümleri kullanarak uçuş parametrelerini (irtifa, hava hızı, Mach sayısı, hücum açısı, vb.) türeten, hava aracı bileşenleri içerisinde en kritiklerinden biridir. Türetilen bu parametreler, hava aracı sistemlerine ve kontrolcülerine girdi oluşturur. Hava veri bilgisayarının çıktılarını kullanan hava aracı sistemlerinin ve kontrolcülerinin, hava aracına entegrasyonundan önce test edilmesi gerekir. Bu amaçla kurulan SEL (Sistem Entegrasyon Laboratuvarı)’de, hava veri bilgisayarı çıktılarına ihtiyaç olmaktadır. Gerçek uçuş senaryolarının SEL’ de gerçek ekipman üzerinde uygulanmasının pratik olmaması, test ortamındaki ekipmanların yetersizliği, test sırasında yüksek maliyetli donanımların ve test ekipmanlarının zarar görme olasılığını en aza indirme gerekliliği gibi nedenlerden dolayı bu ekipmanların benzetim modellerine ihtiyaç duyulmaktadır. Ayrıca, ekipman benzetim modellerini kullanarak aviyonik sistem entegrasyon laboratuvarı maliyetlerini düşürmek de mümkündür. Bu çalışmada; hava veri bilgisayarının benzetim modeli MATLAB/Simulink ortamında oluşturulmuş ve modelin düşük maliyetli bir donanım üzerinde doğrulanması amacıyla PIL (Processor-in-the-Loop) testleri yapılmıştır. Bu çalışma ile beraber; SEL ortamında veya mühendislik simülatörü ile entegre çalışabilen, HIL (Hardware-in-the-loop) simülasyonu için kullanıma hazır, sinyal tabanlı, hava veri bilgisayarı davranışını yüksek oranda sergileyen, çeşitli ekipman hata senaryolarının eklenebildiği bir test aracı amaçlanmaktadır.}},
url = {http://uhuk.org.tr/bildiri.php/UHUK-2020-032}}
author = {Subaşı, Ozan Can and Köktaş, Y., Karasubaşı, M., Bük, Timuçin and Yeniçeri, Ramazan},
title = {{Hava Veri Bilgisayarının Davranış Modellemesi, Donanım Üzerinde Gerçeklenmesi ve SEL Ortamında Kullanımı}},
booktitle = {{8. Ulusal Havacılık ve Uzay Konferansı (UHUK'2020)}},
year = {2020},
month = {September},
pages = {1-14},
abstract = {{Hava veri bilgisayarı, basınç ve sıcaklık sensörlerinden aldığı ölçümleri kullanarak uçuş parametrelerini (irtifa, hava hızı, Mach sayısı, hücum açısı, vb.) türeten, hava aracı bileşenleri içerisinde en kritiklerinden biridir. Türetilen bu parametreler, hava aracı sistemlerine ve kontrolcülerine girdi oluşturur. Hava veri bilgisayarının çıktılarını kullanan hava aracı sistemlerinin ve kontrolcülerinin, hava aracına entegrasyonundan önce test edilmesi gerekir. Bu amaçla kurulan SEL (Sistem Entegrasyon Laboratuvarı)’de, hava veri bilgisayarı çıktılarına ihtiyaç olmaktadır. Gerçek uçuş senaryolarının SEL’ de gerçek ekipman üzerinde uygulanmasının pratik olmaması, test ortamındaki ekipmanların yetersizliği, test sırasında yüksek maliyetli donanımların ve test ekipmanlarının zarar görme olasılığını en aza indirme gerekliliği gibi nedenlerden dolayı bu ekipmanların benzetim modellerine ihtiyaç duyulmaktadır. Ayrıca, ekipman benzetim modellerini kullanarak aviyonik sistem entegrasyon laboratuvarı maliyetlerini düşürmek de mümkündür. Bu çalışmada; hava veri bilgisayarının benzetim modeli MATLAB/Simulink ortamında oluşturulmuş ve modelin düşük maliyetli bir donanım üzerinde doğrulanması amacıyla PIL (Processor-in-the-Loop) testleri yapılmıştır. Bu çalışma ile beraber; SEL ortamında veya mühendislik simülatörü ile entegre çalışabilen, HIL (Hardware-in-the-loop) simülasyonu için kullanıma hazır, sinyal tabanlı, hava veri bilgisayarı davranışını yüksek oranda sergileyen, çeşitli ekipman hata senaryolarının eklenebildiği bir test aracı amaçlanmaktadır.}},
url = {http://uhuk.org.tr/bildiri.php/UHUK-2020-032}}
[T9]
Hasanzade, M., Herekoğlu, Ö., Yeniçeri, R., Koyuncu, E., İnalhan, G.,
"İnsansız Hava Aracı ve Parçacık Filtresi ile RF Sinyal Kaynağının Lokalizasyonu,"
7. Ulusal Havacılık ve Uzay Konferansı (UHUK'2018),
Samsun, 12-14 Eylül 2018.
@inproceedings{yenicerirT9,
author = {Hasanzade, Mehmet and Herekoğlu, Ömer and Yeniçeri, Ramazan and Koyuncu, Emre and İnalhan, Gökhan},
title = {{İnsansız Hava Aracı ve Parçacık Filtresi ile RF Sinyal Kaynağının Lokalizasyonu}},
booktitle = {{7. Ulusal Havacılık ve Uzay Konferansı (UHUK'2018)}},
year = {2018},
month = {September},
pages = {1-8},
abstract = {{Bu çalışmada geniş bir arazide konumu bilinmeyen bir RF sinyal kaynağının, insansız hava aracı (İHA) ile parçacık filtresi kullanılarak konum tespitinin yapılabilmesi amaçlanmıştır. Operasyon, tek bir İHA üzerine takılı RF sinyal gücünü ölçebilen bir sensör ile yapılabilmektedir. Alınan sinyal gücünde karşılaşılan yüksek genlikli gürültü, lokalizasyon probleminin çözümünü zorlaştırmaktadır. Yapılan testlerdeki gürültü ölçüm sonuçları RF sinyalinin uzaklığa bağlı modelinin Friis denkleminden daha gerçekçi oluşturulmasını sağlanmıştır. Bu model ile beraber parçacık filtresi çalışılmış ve simülasyon sonuçları ortaya konmuştur. Yapılan simülasyon sonucunda, 25 m/sn hızla uçan İHA’nın –60 dBm hassasiyetli alıcısı ile 1 W çıkış güçlü kaynaktan yayılan sinyali almaya başlamasından itibaren 91.89 saniye içerisinde 14.23 metre hata ile hedefi lokalize etmiştir.}},
url = {http://uhuk.org.tr/bildiri.php/UHUK-2018-078}}
author = {Hasanzade, Mehmet and Herekoğlu, Ömer and Yeniçeri, Ramazan and Koyuncu, Emre and İnalhan, Gökhan},
title = {{İnsansız Hava Aracı ve Parçacık Filtresi ile RF Sinyal Kaynağının Lokalizasyonu}},
booktitle = {{7. Ulusal Havacılık ve Uzay Konferansı (UHUK'2018)}},
year = {2018},
month = {September},
pages = {1-8},
abstract = {{Bu çalışmada geniş bir arazide konumu bilinmeyen bir RF sinyal kaynağının, insansız hava aracı (İHA) ile parçacık filtresi kullanılarak konum tespitinin yapılabilmesi amaçlanmıştır. Operasyon, tek bir İHA üzerine takılı RF sinyal gücünü ölçebilen bir sensör ile yapılabilmektedir. Alınan sinyal gücünde karşılaşılan yüksek genlikli gürültü, lokalizasyon probleminin çözümünü zorlaştırmaktadır. Yapılan testlerdeki gürültü ölçüm sonuçları RF sinyalinin uzaklığa bağlı modelinin Friis denkleminden daha gerçekçi oluşturulmasını sağlanmıştır. Bu model ile beraber parçacık filtresi çalışılmış ve simülasyon sonuçları ortaya konmuştur. Yapılan simülasyon sonucunda, 25 m/sn hızla uçan İHA’nın –60 dBm hassasiyetli alıcısı ile 1 W çıkış güçlü kaynaktan yayılan sinyali almaya başlamasından itibaren 91.89 saniye içerisinde 14.23 metre hata ile hedefi lokalize etmiştir.}},
url = {http://uhuk.org.tr/bildiri.php/UHUK-2018-078}}
[T8]
Hasanzade, M., Herekoğlu, Ö., Biçer, Y., Üre, N.K., Koyuncu, E., Yeniçeri, R., İnalhan, G.,
"Belirsiz Verici Gücünde RF Sinyal Yayan Kaynakların İnsansız Hava Araçları ile Geniş Ölçekli Ortamda Konumunun Tespiti,"
Otomatik Kontrol Ulusal Toplantısı 2017 (TOK 2017) Bildiri Kitabı,
sayfa 714-719, İstanbul, 21-23 Eylül 2017.
@inproceedings{yenicerirT8,
author = {Hasanzade, Mehmet and Herekoğlu, Ömer and Biçer, Yunus and Üre, Nazım Kemal and Koyuncu, Emre and Yeniçeri, Ramazan and İnalhan, Gökhan},
title = {{Belirsiz Verici Gücünde RF Sinyal Yayan Kaynakların İnsansız Hava Araçları ile Geniş Ölçekli Ortamda Konumunun Tespiti}},
booktitle = {{Otomatik Kontrol Ulusal Toplantısı 2017 (TOK 2017) Bildiri Kitabı}},
year = {2017},
month = {September},
pages = {714-719},
abstract = {{Günümüzde RF sinyal yayan kaynakların farklı ölçüm metotları ile konumlarının belirlenmesi oldukça revaçta bir konudur. Bununla birlikte hali hazırdaki yaklaşımlar, kaynağın verici gücünün belirsiz olduğu durumlarda ve sinyal gücünün gürültüsü nedeniyle geniş ölçekli ortamlarda verimsiz hale gelmektedir. Bu çalışmada RF sinyal yayan kaynakların geniş ölçekli ortamlar ve sinyal verici gücünün net olarak bilinemediği durumlar için RF sinyalinin alınan sinyal gücü (RSS) değerleri kullanılarak insansız hava araçları ile konum tespiti gerçekleştirilmiştir. Bu amaçla, olası sinyal verici güçlerinden yola çıkılarak RF kaynağın sinyal gücünün yapay sinir ağı kullanılarak belirlendiği ve alınan sinyal gücün gürültüsünün konum tespiti üzerindeki etkisini azaltmak amacıyla Genişletilmiş Kalman Filtresi’nin (EKF) uygulandığı konum belirleme mimarisi geliştirilmiştir. Geliştirilen mimari, 3 insansız hava aracı ve 5 km × 5 km alanda yazılım benzetimli test yöntemiyle simüle edilerek ortalama 28.3 m hata ile hedef tespit edilmiştir.}}}
author = {Hasanzade, Mehmet and Herekoğlu, Ömer and Biçer, Yunus and Üre, Nazım Kemal and Koyuncu, Emre and Yeniçeri, Ramazan and İnalhan, Gökhan},
title = {{Belirsiz Verici Gücünde RF Sinyal Yayan Kaynakların İnsansız Hava Araçları ile Geniş Ölçekli Ortamda Konumunun Tespiti}},
booktitle = {{Otomatik Kontrol Ulusal Toplantısı 2017 (TOK 2017) Bildiri Kitabı}},
year = {2017},
month = {September},
pages = {714-719},
abstract = {{Günümüzde RF sinyal yayan kaynakların farklı ölçüm metotları ile konumlarının belirlenmesi oldukça revaçta bir konudur. Bununla birlikte hali hazırdaki yaklaşımlar, kaynağın verici gücünün belirsiz olduğu durumlarda ve sinyal gücünün gürültüsü nedeniyle geniş ölçekli ortamlarda verimsiz hale gelmektedir. Bu çalışmada RF sinyal yayan kaynakların geniş ölçekli ortamlar ve sinyal verici gücünün net olarak bilinemediği durumlar için RF sinyalinin alınan sinyal gücü (RSS) değerleri kullanılarak insansız hava araçları ile konum tespiti gerçekleştirilmiştir. Bu amaçla, olası sinyal verici güçlerinden yola çıkılarak RF kaynağın sinyal gücünün yapay sinir ağı kullanılarak belirlendiği ve alınan sinyal gücün gürültüsünün konum tespiti üzerindeki etkisini azaltmak amacıyla Genişletilmiş Kalman Filtresi’nin (EKF) uygulandığı konum belirleme mimarisi geliştirilmiştir. Geliştirilen mimari, 3 insansız hava aracı ve 5 km × 5 km alanda yazılım benzetimli test yöntemiyle simüle edilerek ortalama 28.3 m hata ile hedef tespit edilmiştir.}}}
[T7]
Tarhan, F., Hasanzade, M., Çetin, A., Biçer, Y., Üre, N.K., Koyuncu, E., Yeniçeri, R., İnalhan, G.,
"Kampüs İHA: 4G Şebeke Destekli Kampüs Güvenliği Artırma Projesi,"
Otomatik Kontrol Ulusal Toplantısı 2017 (TOK 2017) Bildiri Kitabı,
sayfa 655-660, İstanbul, 21-23 Eylül 2017.
@inproceedings{yenicerirT7,
author = {Tarhan, Farabi and Hasanzade, Mehmet and Çetin, Aykut and Biçer, Yunus and Üre, Nazım Kemal and Koyuncu, Emre and Yeniçeri, Ramazan and İnalhan, Gökhan},
title = {{Kampüs İHA: 4G Şebeke Destekli Kampüs Güvenliği Artırma Projesi}},
booktitle = {{Otomatik Kontrol Ulusal Toplantısı 2017 (TOK 2017) Bildiri Kitabı}},
year = {2017},
month = {September},
pages = {655-660},
abstract = {{Üniversite ve fabrika kompleksleri gibi büyük alanlara yayılmış yerleşkelerde, öğrencilerin veya personelin kolayca acil yardım çağrısı yapabilmesi ve ihtiyaç duyduğu yardıma en kısa sürede ulaşacağını bilmesi, kampüs huzuru ve güvenliği açısından oldukça önem taşımaktadır. Bu yayında, oluşabilecek acil yardım çağrılarına cevap vermeye yönelik, dünyadaki teknolojik gelişmelere paralel bir mini insansız hava aracının ve destek sistemlerinin, operasyona elverişli bir şekilde geliştirilmesine yönelik yapılan çalışmalar anlatılmıştır. Bu hava aracı İHA operatörünün sürekli denetimi altında otonom olarak iniş/kalkış yapabilmekte ve acil yardım çağrısının geldiği bölgeye otonom olarak intikal edip faydalı yük donanımı ile görevini gerçekleştirmektedir. Hava aracı faydalı yükünden aldığı bilgiyi sürekli yer kontrol istasyonuna göndermek ve gerektiğinde yeni komutlar almak amacıyla 3G/4G destekli yüksek bant genişliğine sahip bir mobil şebeke modemi ile donatılmıştır. Bu proje kapsamında tam otonom yeteneklere sahip yerli bir otopilot sistemi, dikey iniş kalkış yapabilen mini bir İHA, aviyonik ölçüm sistemleri, haberleşme alt sistemleri, rota planlama arayüzü, faydalı yük kontrol sistemi ve güvenlik operatörü için anlık uyarı arayüzleri geliştirilmiş ve bu çalışmada sunulmuştur.}}}
author = {Tarhan, Farabi and Hasanzade, Mehmet and Çetin, Aykut and Biçer, Yunus and Üre, Nazım Kemal and Koyuncu, Emre and Yeniçeri, Ramazan and İnalhan, Gökhan},
title = {{Kampüs İHA: 4G Şebeke Destekli Kampüs Güvenliği Artırma Projesi}},
booktitle = {{Otomatik Kontrol Ulusal Toplantısı 2017 (TOK 2017) Bildiri Kitabı}},
year = {2017},
month = {September},
pages = {655-660},
abstract = {{Üniversite ve fabrika kompleksleri gibi büyük alanlara yayılmış yerleşkelerde, öğrencilerin veya personelin kolayca acil yardım çağrısı yapabilmesi ve ihtiyaç duyduğu yardıma en kısa sürede ulaşacağını bilmesi, kampüs huzuru ve güvenliği açısından oldukça önem taşımaktadır. Bu yayında, oluşabilecek acil yardım çağrılarına cevap vermeye yönelik, dünyadaki teknolojik gelişmelere paralel bir mini insansız hava aracının ve destek sistemlerinin, operasyona elverişli bir şekilde geliştirilmesine yönelik yapılan çalışmalar anlatılmıştır. Bu hava aracı İHA operatörünün sürekli denetimi altında otonom olarak iniş/kalkış yapabilmekte ve acil yardım çağrısının geldiği bölgeye otonom olarak intikal edip faydalı yük donanımı ile görevini gerçekleştirmektedir. Hava aracı faydalı yükünden aldığı bilgiyi sürekli yer kontrol istasyonuna göndermek ve gerektiğinde yeni komutlar almak amacıyla 3G/4G destekli yüksek bant genişliğine sahip bir mobil şebeke modemi ile donatılmıştır. Bu proje kapsamında tam otonom yeteneklere sahip yerli bir otopilot sistemi, dikey iniş kalkış yapabilen mini bir İHA, aviyonik ölçüm sistemleri, haberleşme alt sistemleri, rota planlama arayüzü, faydalı yük kontrol sistemi ve güvenlik operatörü için anlık uyarı arayüzleri geliştirilmiş ve bu çalışmada sunulmuştur.}}}
[T6]
Koçdoğan, A., Yeniçeri, R., Yalçın, M.E.,
"FPGA Üzerinde MicroBlaze Tabanlı Video İşlemci Tasarımı,"
3. Gömülü Sistemler ve Uygulamaları Sempozyumu (GÖMSİS 2012) Bildiri Kitabı,
sayfa 99-100, İstanbul, 29-30 Kasım 2012.
@inproceedings{yenicerirT6,
author = {Koçdoğan, Abdülkadir and Yeniçeri, Ramazan and Yalçın, Müştak Erhan},
title = {{FPGA Üzerinde MicroBlaze Tabanlı Video İşlemci Tasarımı}},
booktitle = {{3. Gömülü Sistemler ve Uygulamaları Sempozyumu (GÖMSİS 2012) Bildiri Kitabı}},
year = {2012},
month = {November},
pages = {99-100},
abstract = {{Projede, Sahada Programlanabilir Kapı Dizisi (Field Programmable Gate Array – FPGA) üzerinde donanım ve yazılımın birlikte tasarımıyla MicroBlaze tabanlı bir video işlemci gerçeklenmesi amaçlanmıştır. FPGA üzerinde gerçeklenen bir donanım yardımıyla görüntü dizisi bir CMOS sensör modülünden alınmakta, 32 bitlik MicroBlaze mikroişlemcisinde işlenmekte ve FPGA üzerinde gerçeklenen ek bir donanım yardımıyla işlenen görüntü dizisi VGA ekranda görüntülenmektedir. Önerilen donanım, yazılımın esnekliğiyle karmaşık video işleme algoritmalarının gerçeklenmesine izin vermektedir.}}}
author = {Koçdoğan, Abdülkadir and Yeniçeri, Ramazan and Yalçın, Müştak Erhan},
title = {{FPGA Üzerinde MicroBlaze Tabanlı Video İşlemci Tasarımı}},
booktitle = {{3. Gömülü Sistemler ve Uygulamaları Sempozyumu (GÖMSİS 2012) Bildiri Kitabı}},
year = {2012},
month = {November},
pages = {99-100},
abstract = {{Projede, Sahada Programlanabilir Kapı Dizisi (Field Programmable Gate Array – FPGA) üzerinde donanım ve yazılımın birlikte tasarımıyla MicroBlaze tabanlı bir video işlemci gerçeklenmesi amaçlanmıştır. FPGA üzerinde gerçeklenen bir donanım yardımıyla görüntü dizisi bir CMOS sensör modülünden alınmakta, 32 bitlik MicroBlaze mikroişlemcisinde işlenmekte ve FPGA üzerinde gerçeklenen ek bir donanım yardımıyla işlenen görüntü dizisi VGA ekranda görüntülenmektedir. Önerilen donanım, yazılımın esnekliğiyle karmaşık video işleme algoritmalarının gerçeklenmesine izin vermektedir.}}}
[T5]
Yeniçeri, R., Şeker, S.,
"Dalgacık Ayrışımı ile Titreşim Analizine Dayalı Doğalgazlı Su Isıtıcısı İzleme Sistemi,"
20. IEEE Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU 2012) Bildiri Kitabı,
sayfa 1-4, Fethiye, 18-20 Nisan 2012.
@inproceedings{yenicerirT5,
author = {Yeniçeri, Ramazan and Şeker, Serhat},
title = {{Dalgacık Ayrışımı ile Titreşim Analizine Dayalı Doğalgazlı Su Isıtıcısı İzleme Sistemi}},
booktitle = {{20. IEEE Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU 2012) Bildiri Kitabı}},
year = {2012},
month = {April},
pages = {1-4},
abstract = {{Bu bildiride, mekanik bir sistem olan ev tipi doğalgazlı su ısıtıcısının çalışma durumunu izlemek için bir dalgacık analizi uygulaması sunulmaktadır. Bu kestirimci bakım uygulamasında mekanik sisteme ait titreşim işaretinin kaydı ayrık zamanlı dalgacık ayrışımı kullanılarak analiz edilmiştir. Titreşim kaydı için düşük maliyetli bir mikrofondan yararlanılmıştır. Daha sonra önerilen uygulamanın Simulink modeli kurulmuştur. Bu model, gerçek zamanlı gözlem yapma imkanını sağlamaktadır. Bu bildirideki titreşime dayalı kestirimci bakım yaklaşımı kendi mekanik durumunu gözleyebilen akıllı su ısıtıcılarının geliştirilmesine katkı sağlayacaktır.}},
doi = {https://doi.org/10.1109/SIU.2012.6204577}}
author = {Yeniçeri, Ramazan and Şeker, Serhat},
title = {{Dalgacık Ayrışımı ile Titreşim Analizine Dayalı Doğalgazlı Su Isıtıcısı İzleme Sistemi}},
booktitle = {{20. IEEE Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU 2012) Bildiri Kitabı}},
year = {2012},
month = {April},
pages = {1-4},
abstract = {{Bu bildiride, mekanik bir sistem olan ev tipi doğalgazlı su ısıtıcısının çalışma durumunu izlemek için bir dalgacık analizi uygulaması sunulmaktadır. Bu kestirimci bakım uygulamasında mekanik sisteme ait titreşim işaretinin kaydı ayrık zamanlı dalgacık ayrışımı kullanılarak analiz edilmiştir. Titreşim kaydı için düşük maliyetli bir mikrofondan yararlanılmıştır. Daha sonra önerilen uygulamanın Simulink modeli kurulmuştur. Bu model, gerçek zamanlı gözlem yapma imkanını sağlamaktadır. Bu bildirideki titreşime dayalı kestirimci bakım yaklaşımı kendi mekanik durumunu gözleyebilen akıllı su ısıtıcılarının geliştirilmesine katkı sağlayacaktır.}},
doi = {https://doi.org/10.1109/SIU.2012.6204577}}
[T4] Gönen, B., Yeniçeri, R., Ayhan, T., Yalçın, M.E., "FPGA Üzerinde İzgesel Bastırma Yöntemi ile Konuşma İşaretinden Gürültü Giderme," IEEE 19. Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU 2011) Bildiri Kitabı, sayfa 598-601, Antalya, 20-22 Nisan 2011.
@inproceedings{yenicerirT4,
author = {Gönen, Burak and Yeniçeri, Ramazan and Ayhan, Tuba and Yalçın, Müştak Erhan},
title = {{FPGA Üzerinde İzgesel Bastırma Yöntemi ile Konuşma İşaretinden Gürültü Giderme}},
booktitle = {{IEEE 19. Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU 2011) Bildiri Kitabı}},
year = {2011},
month = {April},
pages = {598-601},
abstract = {{Konuşma işaretinden gürültü giderme, ses işleme uygulamalarının önemli bir problemi olagelmiştir. Bu bildiride, işitme cihazları gibi mikrofon ve hoparlörün birbirine çok yakın olduğu, tek mikrofonlu bir sistemde kullanılabilecek bir gürültü giderme algoritması FPGA üzerinde gerçeklenmiştir. Frekans tabanlı olan bu gürültü giderme algoritmasında, gürültünün kestirimi uyarlamalı olarak gerçekleştirilmiş, böylece sistemin ortam değişikliklerinde de konuşma işaretinden gürültüyü giderebilmesi sağlanmıştır.}},
doi = {https://doi.org/10.1109/SIU.2011.5929721}}
author = {Gönen, Burak and Yeniçeri, Ramazan and Ayhan, Tuba and Yalçın, Müştak Erhan},
title = {{FPGA Üzerinde İzgesel Bastırma Yöntemi ile Konuşma İşaretinden Gürültü Giderme}},
booktitle = {{IEEE 19. Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU 2011) Bildiri Kitabı}},
year = {2011},
month = {April},
pages = {598-601},
abstract = {{Konuşma işaretinden gürültü giderme, ses işleme uygulamalarının önemli bir problemi olagelmiştir. Bu bildiride, işitme cihazları gibi mikrofon ve hoparlörün birbirine çok yakın olduğu, tek mikrofonlu bir sistemde kullanılabilecek bir gürültü giderme algoritması FPGA üzerinde gerçeklenmiştir. Frekans tabanlı olan bu gürültü giderme algoritmasında, gürültünün kestirimi uyarlamalı olarak gerçekleştirilmiş, böylece sistemin ortam değişikliklerinde de konuşma işaretinden gürültüyü giderebilmesi sağlanmıştır.}},
doi = {https://doi.org/10.1109/SIU.2011.5929721}}
[T3]
Ergünay, S., Yeniçeri, R., Yalçın, M.E.,
"Hücresel Yapay Sinir Ağı Hücresi Olarak Bir Relaksasyon Osilatörünün FPGA Üzerinde Donanım-Yazılım Ortak Tasarımı ve Gerçeklenmesi,"
Akıllı Sistemlerde Yenilikler ve Uygulamaları Sempozyumu (ASYU 2010) Bildiri Kitabı,
sayfa 192-195, Kayseri, 21-24 Haziran 2010.
@inproceedings{yenicerirT3,
author = {Ergünay, Selman and Yeniçeri, Ramazan and Yalçın, Müştak Erhan},
title = {{Hücresel Yapay Sinir Ağı Hücresi Olarak Bir Relaksasyon Osilatörünün FPGA Üzerinde Donanım-Yazılım Ortak Tasarımı ve Gerçeklenmesi}},
booktitle = {{Akıllı Sistemlerde Yenilikler ve Uygulamaları Sempozyumu (ASYU 2010) Bildiri Kitabı}},
year = {2010},
month = {June},
pages = {192-195},
abstract = {{Bu bildiride, robot yönlendirme problemine doğrusal olmayan uzay-zaman dalgaları ile çözüm üretmekte kullanılan bir hücresel doğrusal olmayan ağa ait hücrenin, FPGA üzerinde gerçeklenen yazılım-donanım ortak tasarımı tanıtılmaktadır. Tasarımın donanım parçası ayrıklaştırılmış bir gevşemeli osilatörün (relaksasyon osilatörünün) sayısal devre gerçeklemesi iken yazılım parçası 32-bitlik mikroişlemci tarafından çalıştırılan ve bu devreyi kontrol eden C kodudur.}}}
author = {Ergünay, Selman and Yeniçeri, Ramazan and Yalçın, Müştak Erhan},
title = {{Hücresel Yapay Sinir Ağı Hücresi Olarak Bir Relaksasyon Osilatörünün FPGA Üzerinde Donanım-Yazılım Ortak Tasarımı ve Gerçeklenmesi}},
booktitle = {{Akıllı Sistemlerde Yenilikler ve Uygulamaları Sempozyumu (ASYU 2010) Bildiri Kitabı}},
year = {2010},
month = {June},
pages = {192-195},
abstract = {{Bu bildiride, robot yönlendirme problemine doğrusal olmayan uzay-zaman dalgaları ile çözüm üretmekte kullanılan bir hücresel doğrusal olmayan ağa ait hücrenin, FPGA üzerinde gerçeklenen yazılım-donanım ortak tasarımı tanıtılmaktadır. Tasarımın donanım parçası ayrıklaştırılmış bir gevşemeli osilatörün (relaksasyon osilatörünün) sayısal devre gerçeklemesi iken yazılım parçası 32-bitlik mikroişlemci tarafından çalıştırılan ve bu devreyi kontrol eden C kodudur.}}}
[T2]
Yeniçeri, R., Kılıç, V., Yalçın, M.E.,
"Uzay Zaman Dalgalarına Dayalı Yeni Bir Hedef Takip Algoritması,"
IEEE 18. Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU 2010) Bildiri Kitabı,
sayfa 562-565, Diyarbakır, 22-24 Nisan 2010.
@inproceedings{yenicerirT2,
author = {Yeniçeri, Ramazan and Kılıç, Volkan and Yalçın, Müştak Erhan},
title = {{Uzay Zaman Dalgalarına Dayalı Yeni Bir Hedef Takip Algoritması}},
booktitle = {{IEEE 18. Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU 2010) Bildiri Kitabı}},
year = {2010},
month = {April},
pages = {562-565},
abstract = {{Bu bildiride, üzerinde engeller barındıran iki boyutlu uzayda seçilen bir nokta ile diğer tüm noktalar arasındaki en kısa yolları bulma problemini çözen bir Hücresel Doğrusal Olmayan Ağ'ın modeli, gerçeklenmesi ve en kısa yoldan hedefe ulaştıracak yönlendirme algoritması sunulmuştur. Ardından, uygulama için özel olarak oluşturulan bir platform üzerinde takipçi robotun, yine bu bildiride sunulan takip algoritmasıyla hedef robotu takibi senaryosu gerçekleştirilmiştir.}},
doi = {https://doi.org/10.1109/SIU.2010.5652251}}
author = {Yeniçeri, Ramazan and Kılıç, Volkan and Yalçın, Müştak Erhan},
title = {{Uzay Zaman Dalgalarına Dayalı Yeni Bir Hedef Takip Algoritması}},
booktitle = {{IEEE 18. Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU 2010) Bildiri Kitabı}},
year = {2010},
month = {April},
pages = {562-565},
abstract = {{Bu bildiride, üzerinde engeller barındıran iki boyutlu uzayda seçilen bir nokta ile diğer tüm noktalar arasındaki en kısa yolları bulma problemini çözen bir Hücresel Doğrusal Olmayan Ağ'ın modeli, gerçeklenmesi ve en kısa yoldan hedefe ulaştıracak yönlendirme algoritması sunulmuştur. Ardından, uygulama için özel olarak oluşturulan bir platform üzerinde takipçi robotun, yine bu bildiride sunulan takip algoritmasıyla hedef robotu takibi senaryosu gerçekleştirilmiştir.}},
doi = {https://doi.org/10.1109/SIU.2010.5652251}}
[T1]
Koyuncu, E., Ceylan, O., Yeniçeri, R.,
"Bilgisayarla Görü Tabanlı, Cisim Yörünge Doğrultusu İzleyen Robot Kol Tasarımı,"
Otomatik Kontrol Türk Milli Komitesi, Otomatik Kontrol Ulusal Toplantısı (TOK’05) Bildiri Kitabı,
sayfa 291-296, İstanbul, 2-3 Haziran 2005.
@inproceedings{yenicerirT1,
author = {Koyuncu, Emre and Ceylan, Osman and Yeniçeri, Ramazan},
title = {{Bilgisayarla Görü Tabanlı, Cisim Yörünge Doğrultusu İzleyen Robot Kol Tasarımı}},
booktitle = {{Otomatik Kontrol Türk Milli Komitesi, Otomatik Kontrol Ulusal Toplantısı (TOK’05) Bildiri Kitabı}},
year = {2005},
month = {June},
pages = {291-296},
abstract = {{Bu çalışmada, hareketli bir cismin yörünge doğrultusunu kamera ve kamera görüntülerini işleyen bilgisayar tabanlı bir yazılım ile izleyen iki eksenli bir robot kol tasarımında izlenen temel yöntemler ve karşılaşılan problemlere sunulan temel çözümler ele alınmış ve uygulama ile ilgili gelecek çalışmalara değinilmiştir.}},
keywords = {{robot, cisim yörüngesi izleme, bilgisayarla görü, motor denetimi}}}
author = {Koyuncu, Emre and Ceylan, Osman and Yeniçeri, Ramazan},
title = {{Bilgisayarla Görü Tabanlı, Cisim Yörünge Doğrultusu İzleyen Robot Kol Tasarımı}},
booktitle = {{Otomatik Kontrol Türk Milli Komitesi, Otomatik Kontrol Ulusal Toplantısı (TOK’05) Bildiri Kitabı}},
year = {2005},
month = {June},
pages = {291-296},
abstract = {{Bu çalışmada, hareketli bir cismin yörünge doğrultusunu kamera ve kamera görüntülerini işleyen bilgisayar tabanlı bir yazılım ile izleyen iki eksenli bir robot kol tasarımında izlenen temel yöntemler ve karşılaşılan problemlere sunulan temel çözümler ele alınmış ve uygulama ile ilgili gelecek çalışmalara değinilmiştir.}},
keywords = {{robot, cisim yörüngesi izleme, bilgisayarla görü, motor denetimi}}}
Theses
[Z3]
Yeniçeri, R.,
"Implementations of Novel Cellular Nonlinear and Cellular Logic Networks and Their Applications,"
Istanbul Technical University, Graduate School of Science, Engineering and Technology, Ph.D. Thesis,
Istanbul, October 2015.
[Z2]
Yeniçeri, R.,
"Yol Bulma Uygulamaları için Bir Hücresel Yapay Sinir Ağının Sayısal Tasarımı ve Gerçeklenmesi,"
Istanbul Technical University, Graduate School of Science, Engineering and Technology, M.Sc. Thesis,
Istanbul, June 2009. (Turkish)
[Z1]
Yeniçeri, R.,
"CMOS Görüntü Sensörü ve FPGA ile Sayısal Fotoğraf Makinesi Gerçeklenmesi,"
Istanbul Technical University, Faculty of Electrical and Electronics Engineering, Graduation Project,
Istanbul, May 2007. (Turkish)
Others (Abstracts, Poster Presentations)
[O8]
Çiçek M., Yeniçeri R.,
"Havadan Ağ ile Oluşturulmuş Nesnelerin İnterneti Ağı için Yukarı Yönlü İletişimin Sınır Bilişim ile Optimizasyonu,"
10. Uluslararası Mühendislik Mimarlık ve Tasarım Kongresi,
online, 24-25 Aralık, 2022.
[O7]
Inalhan G., Koyuncu E., Üre N.K., Yeniçeri R.,
"Flightdeck Automation with 4D Trajectory Management and Control for the Next Generation ATM System,"
1st IEEE Conference on Control Technology and Applications (CCTA 2017), Workshop on Guidance, Navigation and Control Applications in the Aerospace Industry: Current Problems and Modern Solutions,
presented in tutorial workshops, Kohala Coast, Hawaii, August 27-30, 2017.
[O6]
Yeniçeri R., Gönen B., Yalçın M.E.,
"FPGA Üzerinde Gerçek Zamanlı Bir İzgesel Konuşma İyileştirici Gerçeklemesi,"
IEEE 19. Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU 2011),
demo oturumunda sunulan, Antalya, 20-22 Nisan 2011. (Turkish)
[O5]
Yeniçeri R., Kılıç V., Yalçın M.E.,
"An On-line Test Setup of CNN Based Real-time Mobile Robot Navigation Application,"
Proc. of 12th International Workshop on Cellular Nanoscale Networks and Applications (CNNA 2010),
p. 1-1, Berkeley, USA, February 3-5, 2010.
[O4]
Yeniçeri R., Yalçın M.E.,
"A Testbed of 2D Locally Coupled Relaxation Oscillators for Spiral Waves Generation,"
Abstract Booklet of 4th International Scientific Conference on Physics and Control (PHYSCON 2009),
p. 87, Catania, Italy, September 1-4, 2009.
[O3]
Yeniçeri R., Usta A., Yalçın M.E.,
"ITUcam, FPGA Tabanlı Görüntü Yakalama ve İşleme Kartı Gerçeklemesi,"
1. Gömülü Sistemler ve Uygulamaları Sempozyumu (GÖMSİS 2008) Özet Kitabı,
sayfa 24, İstanbul, 3-5 Kasım 2008. (Turkish)
[O2]
Yeniçeri R., Yalçın M.E.,
"A Programmable Hardware for Exploring Spatiotemporal Waves in Real-time,"
Proc. of 11th International Workshop on Cellular Neural Networks and their Applications (CNNA 2008),
p. 7, Santiago de Compostela, Spain, July 14-16, 2008.
[O1]
Koyuncu E., Ceylan O., Yeniçeri R.,
"Kamera Denetimli Yapay Sinir Ağları ile Hareketli Cisim Yörüngesi İzleyen Zeki Taret Savunma Sistemi Tasarımı,"
Kara Harp Okulu, Savunma Bilimleri Enstitüsü, 1. Savunma Bilimleri Araştırmaları Yarışması Eser Özetleri Kitabı,
Ankara, 13 Mart 2006. (Turkish)