OLDER RESEARCH (Prior to Joining ITU)
My PhD dissertation research investigated solutions to relax the barriers of GPU architectures that limit the applicability of GPUs. The goal of my dissertation was to open up the benefits of GPU computing to a much wider range of general-purpose applications. It proposed Hierarchical Queuing Locks (HQL), a novel hardware-based synchronization mechanism to enable scalable and efficient fine-grained synchronization on GPUs, thus extending the applicability of GPUs to the applications whose portability tightly coupled to the underlying synchronization support. Building on HQL, it also proposed Scalar waving (SW), a new micro-architectural design to exploit the identical instruction execution within a SIMD group to better utilize the SIMD units on GPUs. Scalar waving aims improve the efficiency of SIMD execution and better tolerate the applications possessing irregular control flow.
My research experience goes back to my Master’s study. My research for my Master thesis focused on wrong path memory effects on shared-memory multiprocessor and chip multiprocessor systems.