Microelectronic Analog Circuit Design Homework #2 & #3

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Deadline for Homework #2: December 14^th, 2009, Monday
Deadline for Homework #3: December 18^th, 2009, Friday

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Homework #2

For the single-ended current-mirror-load differential amplifier (see Page 73 of the handouts), the following are given:

m_n=300 cm²/(V.s), m_p=100 cm²/(V.s), m_nC_ox=30mA/V², m_pC_ox=10mA/V², V_Tn=0.7V, V_Tp=-0.8V, l_n=0.01V^-1, l_p=0.02V^-1, I_SS=20mA, (W/L)_1,2=30, (W/L)_3,4=50.

Assuming that I_SS is supplied from an nMOS transistor in saturation with a fixed bias and ignoring body effect, determine the worst-case CMRR in dB if |D(W/L)_1,2|_max=1, |Dm_n|_max=30 cm²/(V.s) and |DV_Tn|_max=50mV.

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Homework #3

The circuit in Midterm Exam #1 of 2002 (problem | solution) will be simulated using the LEVEL 1 parameters,
nMOS: KP=135U, VTO=0.7, LAMBDA=0.05
pMOS: KP=40U, VTO=-0.8, LAMBDA=0.1

Use the aspects (W & L), V_B, I and V_IN (DC part of v_IN) values supplied in the solutions of the exam and with aid of SPICE determine the following:

I_D1 and I_D2 (DC drain currents of M1 and M2)

V_D1 (DC Drain voltage of M1)

P_DC (DC power consumption - drawn from V_DD)

overdrive voltages of M5 and M6

A_v (Small signal voltage gain)

the output voltage swing limits V_OUTmin and V_OUTmax

To what extent do these values meet the specifications dictated in (a) and found in (b) of the exam problem? Also, add your comments.

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