Low-Voltage Analog Integrated Circuit Design
Design Project #2
Deadline : January 18th, 2010, Monday
A rail-to-rail CMOS operational amplifier will be designed and simulated.

As the input stage, you will use one of the constant-Gm rail-to-rail input stages you designed and simulated yourself before (as Project #1). Use the VDD value you used for Project #1.

You can use any type of rail-to-rail output stage as your output stage.

The load will be a purely capacitive one with value CL=1pF. Don't forget to keep this capacitor always connected to the output

The open-loop gain (Av) and phase margin (PM) of the opamp must be >70dB and >70o, respectively, for the whole common-mode input range.

(You are expected to compensate the operational amplifier accordingly)

Although the main specifications are given only for Av and PM, you are still expected to try to optimize the gain-bandwidth, slew rate and keep area and power consumption within acceptable limits.

You can choose and use the model parameters (an adequate model is preferred) of a suitable CMOS process and an appropriate simulator (You'd better prefer the same ones you used for Project #1)

You must conduct appropriate simulations to determine some important values/characteristics of your operational amplifier (listed below) and supply them in the report.
  • |Av|-ViCM curve
  • GBW-ViCM curve
  • PM-ViCM curve
  • Offset voltage (Vos) for ViCM=VDD/2
  • Slew rate (SR)

    Also,
  • Apply a rail-to-rail (or at least a peak-to-peak amplitude very close to that) 1kHz sine-wave to the input of the unity-gain (buffer) configuration of the opamp and obtain the output waveform to show that the opamp is really operating rail-to-rail.
  • Apply a rail-to-rail 1MHz square-wave to the input of the same buffer and obtain the output waveform to reveal the large-signal behaviour (speed + linearity + stability) of the opamp.
  • It will be a PLUS for you, if you give the "low voltage" operation limits (e.g. reveal the performance for lower VDD voltages) of your circut.
  • It will be also appreciated if you connect a resistive load at the output (in parallel with the capacitive load) of the buffer and show the rail-to-rail operation for this condition. Try to keep the load resistance as low as possible and present the "limit" acceptable result (the result for the lowest load resistance value that can be tolerated by the circuit).
    (Of course, since your original opamp design will not be based on this condition, don't be ashamed if you can't obtain a good result for low resistance values. You can make minor modifications though, to improve the performance for this condition)
    Note: As can be guessed, the load resistance should be connected between the output and ground if you use double supplies (VDD and VSS). However, for a single-supply case (VDD), the actual "ground" of the opamp will be VDD/2, so one terminal of the load resistance should be connected to VDD/2.
    (This is not a problem for the load capacitance, since for both types of connection the capacitor will draw zero DC current)
  • In your project report, explain the methodology you tracked during the design and simulation processes.
  • Don't forget to explain the difficulties you coped with during the design/simulation processes and explain (or try to guess) the possible causes of those difficulties.