Intel 8086 Family Architecture

        General Purpose Registers               Segment Registers

        AH/AL  AX  (EAX)  Accumulator            CS     Code Segment
        BH/BL  BX  (EBX)  Base                   DS     Data Segment
        CH/CL  CX  (ECX)  Counter                SS     Stack Segment
        DH/DL  DX  (EDX)  Data                   ES     Extra Segment
                                                (FS)    386 and newer
        (Exx) indicates 386+ 32 bit register    (GS)    386 and newer


        Pointer Registers                       Stack Registers

        SI (ESI)  Source Index                  SP (ESP)  Stack Pointer
        DI (EDI)  Destination Index             BP (EBP)  Base Pointer
        IP        Instruction Pointer

        Status Registers

        FLAGS Status Flags   (see FLAGS)

        Special Registers (386+ only)

        CR0     Control Register 0        DR0    Debug Register 0
        CR2     Control Register 2        DR1    Debug Register 1
        CR3     Control Register 3        DR2    Debug Register 2
                                          DR3    Debug Register 3
        TR4     Test Register 4           DR6    Debug Register 6
        TR5     Test Register 5           DR7    Debug Register 7
        TR6     Test Register 6
        TR7     Test Register 7
        
        Register          Default Segment    Valid Overrides

        BP                      SS              DS, ES, CS
        SI or DI                DS              ES, SS, CS
        DI strings              ES              None
        SI strings              DS              ES, SS, CS


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