For presentation purposes only

This is a simulator for a fictional design of a RISC microprocessor. Please contact @dagvadorj for more details!
r0 r1 r2 r3
00000000 00000000 00000000 00000000
pc
state
fetch > decode > execute

Instruction set

in 0a r1 <- m[0a]
out 0a m[0a] <- r1
jmp 0a pc <- 0a
add r1 r2 r3 r3 <- r1 + r2
sub r1 r2 r3 r3 <- r1 - r2
shl r1 r2 r3 r3 <- r1 << r2
shr r1 r2 r3 r3 <- r1 >> r2
and r1 r2 r3 r3 <- r1 & r2
or r1 r2 r3 r3 <- r1 | r2
xor r1 r2 r3 r3 <- r1 ^ r2
not r1 r2 r2 <- ~r1