--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   19:11:48 12/16/2009
-- Design Name:   
-- Module Name:   C:/Documents and Settings/Administrator/Belgelerim/Dersler_YRD/SSTU/SSTU09-10/vhdl/sstu1/tb.vhd
-- Project Name:  sstu1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ao_logic
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tb IS
END tb;
 
ARCHITECTURE behavior OF tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ao_logic
    PORT(
         IN1 : IN  std_logic;
         IN2 : IN  std_logic;
         IN3 : IN  std_logic;
         IN4 : IN  std_logic;
         OUT3 : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal IN1 : std_logic := '0';
   signal IN2 : std_logic := '0';
   signal IN3 : std_logic := '0';
   signal IN4 : std_logic := '0';

 	--Outputs
   signal OUT3 : std_logic;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: ao_logic PORT MAP (
          IN1 => IN1,
          IN2 => IN2,
          IN3 => IN3,
          IN4 => IN4,
          OUT3 => OUT3
        );
 
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
--   constant <clock>_period := 1ns;
-- 
--   <clock>_process :process
--   begin
--		<clock> <= '0';
--		wait for <clock>_period/2;
--		<clock> <= '1';
--		wait for <clock>_period/2;
--   end process;
-- 
--
--   -- Stimulus process
--   stim_proc: process
--   begin		
--      -- hold reset state for 100ms.
--      wait for 100ms;	
--
--      wait for <clock>_period*10;
--      wait;
--		
--   end process;

      -- insert stimulus here
test: process
begin
IN1<='1';		
IN2<='1';	
IN3<='1';	
IN4<='1';	

wait for 10ms;
IN1<='0';		
IN2<='0';	
IN3<='0';	
IN4<='0';	
      wait;
		
   end process;

END;
