sstu1 Project Status (12/16/2009 - 19:05:08)
Project File: | sstu1.ise | Implementation State: | Synthesized
Module Name: | ao_logic |

- Errors:

No Errors
Target Device: | xc3s500e-5cp132 |

- Warnings:

No Warnings
Product Version: | ISE 11.1 |

- Routing Results:

Design Goal: | Balanced |

- Timing Constraints:

Design Strategy: | Xilinx Default (unlocked) |

- Final Timing Score:

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of Slices | 1 | 4656 | 0%
Number of 4 input LUTs | 1 | 9312 | 0%
Number of bonded IOBs | 5 | 92 | 5%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Çar 16. Ara 19:05:06 2009 | 0 | 0 | 0
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated

Date Generated: 12/16/2009 - 19:25:50