Release 11.1 - xst L.33 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.13 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.13 secs
 
--> Reading design: ao_logic.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "ao_logic.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "ao_logic"
Output Format                      : NGC
Target Device                      : xc3s500e-5-cp132

---- Source Options
Top Module Name                    : ao_logic
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Library Search Order               : ao_logic.lso
Keep Hierarchy                     : NO
Netlist Hierarchy                  : as_optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Documents and Settings/Administrator/Belgelerim/Dersler_YRD/SSTU/SSTU09-10/vhdl/sstu1/AND_gate.vhd" in Library work.
Architecture behavioral of Entity and_gate is up to date.
Compiling vhdl file "C:/Documents and Settings/Administrator/Belgelerim/Dersler_YRD/SSTU/SSTU09-10/vhdl/sstu1/OR_gate.vhd" in Library work.
Architecture behavioral of Entity or_gate is up to date.
Compiling vhdl file "C:/Documents and Settings/Administrator/Belgelerim/Dersler_YRD/SSTU/SSTU09-10/vhdl/sstu1/AND-OR-logic.vhd" in Library work.
Entity <ao_logic> compiled.
Entity <ao_logic> (Architecture <LogicOperation>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <ao_logic> in library <work> (architecture <LogicOperation>).

Analyzing hierarchy for entity <AND_gate> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <OR_gate> in library <work> (architecture <behavioral>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <ao_logic> in library <work> (Architecture <LogicOperation>).
Entity <ao_logic> analyzed. Unit <ao_logic> generated.

Analyzing Entity <AND_gate> in library <work> (Architecture <behavioral>).
Entity <AND_gate> analyzed. Unit <AND_gate> generated.

Analyzing Entity <OR_gate> in library <work> (Architecture <behavioral>).
Entity <OR_gate> analyzed. Unit <OR_gate> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <AND_gate>.
    Related source file is "C:/Documents and Settings/Administrator/Belgelerim/Dersler_YRD/SSTU/SSTU09-10/vhdl/sstu1/AND_gate.vhd".
Unit <AND_gate> synthesized.


Synthesizing Unit <OR_gate>.
    Related source file is "C:/Documents and Settings/Administrator/Belgelerim/Dersler_YRD/SSTU/SSTU09-10/vhdl/sstu1/OR_gate.vhd".
Unit <OR_gate> synthesized.


Synthesizing Unit <ao_logic>.
    Related source file is "C:/Documents and Settings/Administrator/Belgelerim/Dersler_YRD/SSTU/SSTU09-10/vhdl/sstu1/AND-OR-logic.vhd".
Unit <ao_logic> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <ao_logic> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ao_logic, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                           Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ao_logic.ngr
Top Level Output File Name         : ao_logic
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 5

Cell Usage :
# BELS                             : 1
#      LUT4                        : 1
# IO Buffers                       : 5
#      IBUF                        : 4
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s500ecp132-5 

 Number of Slices:                        1  out of   4656     0%  
 Number of 4 input LUTs:                  1  out of   9312     0%  
 Number of IOs:                           5
 Number of bonded IOBs:                   5  out of     92     5%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 5.753ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 4 / 1
-------------------------------------------------------------------------
Delay:               5.753ns (Levels of Logic = 3)
  Source:            IN1 (PAD)
  Destination:       OUT3 (PAD)

  Data Path: IN1 to OUT3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.106   0.509  IN1_IBUF (IN1_IBUF)
     LUT4:I0->O            1   0.612   0.357  G3/X1 (OUT3_OBUF)
     OBUF:I->O                 3.169          OUT3_OBUF (OUT3)
    ----------------------------------------
    Total                      5.753ns (4.887ns logic, 0.866ns route)
                                       (84.9% logic, 15.1% route)

=========================================================================


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.48 secs
 
--> 

Total memory usage is 164276 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

