Informations about VLSI 2 Course


Content : Introduction to the CADENCE DFII VLSI design environment. Examining the VLSI design flow. System level architectural design. VERILOG and VHDL hardware description languages (HDL). HDL codes for synthesis. Logic design and verification. Usage of VERILOG-XL environment. Automatic synthesis of logic design. Synopsys environment. Introduction to standard-cell libraries and their usage. Standard-cell placement & routing. Full custom design strategies. Layout design in CADENCE-ARTIST design environment. Chip-level floorplanning, clock and power distribution. VLSI test methods and design for testability.
 
References :

VHDL
      Douglas L. Perry
      McGraw-Hill Inc, 1991.

The VERILOG HDL,
             Donald E.Thomas & Philip R. Moorby
             KAP, 1994.

VHDL Modeling for Digital Design Synthesis
                        Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
                        Kluwer Academic Pub.1995

A guide to VHDL, 2nd Edition
                       Stanley Mazor, Patricia Langstraat
                       Kluwer Academic Pub.1993

VHDL Compiler Reference Manual
                       Sysnopsys Inc,1992

Verilog-HDL Reference Manual
                      Cadence Inc

Verilog-HDL Style Guide
                      Cadence Inc

 
Hours : Tuesday 14:00 - 17:00

 

Weights of the Exams:

Grading Policy     Date
Homeworks (1-7) : 7 x %4  
Quizs (1-3) : 3 x %4  
Midterms(1-2) : 2 x %10  
Final : %20  
Term Project : %20  

 

Homeworks    Answers  Projects
0.35um CMOS Model Device Param. 0.6um CMOS Device Model Param. 0.8um CMOS Device Model Param.
0.35um CMOS DRC Rules 0.6um CMOS DRC Rules 0.8um CMOS DRC Rules
0.35um CMOS Process Doc 0.6um CMOS Process Doc. 0.8um CMOS Process Doc