Informations about VLSI 1 Course
Content : VLSI design techniques and foundations. ASIC design, FPGA, gate-arrays and standard-cells. Full custom design approaches. Floorplanning in chip-level. Separation of the system building blocks. High-performance digital building block design. Standard cell placement & routing algorithms. Verification of design, logic simulation, timing simulation, transistor level simulation, post-layout simulation. Design techniques for regular building blocks: memory arrays, PLAs. Testable system design techniques. Reliability
 
References :

PRINCIPLES OF CMOS VLSI DESIGN
                 Neil H. E. Weste, Kamran Eshraghian
                 Addison-Wesley Pub. 2nd ed. 1992

CMOS DIGITAL INTEGRATED CIRCUITS: ANALYSIS AND DESIGN
                                                                     S.M. Kang, Y. Leblebici,1994

VLSI Engineering,
            T. Dillinger
            Prentice Hall ,1988

Advanced Simulation and Test Methodologies For VLSI Design
                                                                    Gordon Russel and L. Sayers
                                                                    Van Nostrand Reinhold,1989

Algorithms For VLSI Physical Design Automation
                                                  Naveed A. Sherwani
                                                 Kluwer Academic Pub.1993

Digital System Engineering
                W.J. Dally and J.W. Poulton
                Cambridge University Press, 1998.

High Speed CMOS Design Styles
                            K. Bernstein, et al,
                          Kluwer Academic Publishers, 1998.

High-Performance System Design: Circuits and Logic
                                          V.G. Oklobdzija
                                           IEEE Press, 1999.

Low-Power CMOS Design
              A. Chandrakasan and R. Brodersen,
                                        IEEE Press, 1998.

 
Hours : Tuesday 14:00 - 17:00

 

Weights of the Exams:

Grading Policy     Date
Homeworks (1-7) : 7 x %4  
Quizs (1-3) : 3 x %4  
Midterms(1-2) : 2 x %10  
Final : %20  
Term Project : %20  

 

Homeworks    Answers  Projects
0.35um CMOS Model Device Param. 0.6um CMOS Device Model Param. 0.8um CMOS Device Model Param.
0.35um CMOS DRC Rules 0.6um CMOS DRC Rules 0.8um CMOS DRC Rules
0.35um CMOS Process Doc 0.6um CMOS Process Doc. 0.8um CMOS Process Doc