Osicom Technologies

DIRECT-DIGITAL FREQUENCY SYNTHESIS

...a basic tutorial

Osicom Technologies Inc. Technical Staff

Introduction

The term "frequency synthesizer" applies to an active electronic device that accepts some reference frequency and then generates one or more new ones as commanded by a control word or method, whereby the stability, accuracy, and spectral purity of the output correlates with the performance of the input reference (Figure 1). That is, if the reference is accurate to one part in 10-7, the output at the new frequency will be the same. The quality of the frequency synthesizer is judged upon many other performance factors, including the degree to which the crystal's spectral purity qualities are degraded by the synthesis process, but to be a synthesizer there must be perfect correlation between the accuracy of the reference and that of the output.

Figure 1

Three conventional frequency synthesis techniques by which this function can be accomplished are common throughout the industry: phase-lock loop (PLL, or "indirect"), mix/filter/divide (direct-analog), and direct-digital. Each of these methodologies has advantages and disadvantages, hence each application requires selection based upon the most acceptable combination of compromises.

Direct-analog synthesis (Figure 2), also called mix/filter, uses echelons of multiplication , division, and other mathematical manipulations to produce the desired new frequency. The process is called "direct" because the error correction process is avoided, hence the quality of the output correlates directly with the quality of the input. Phase noise is typically excellent because of the direct process, particularly close to the carrier, and switching speed can be very fast. It's an expensive process, however, and finer steps require additional circuitry that further increase complexity and cost.

Figure 2

One potentially important characteristic of a mix/filter synthesizer is its ability to return to any frequency at the point in phase at which it would have been had it never departed - a trait called "phase memory". As a mix/filter design switches among frequencies it appears like a switched bank of oscillators. In certain track-while-scan and similar radars, for instance, that is a useful attribute. Unfortunately, a broadband mix/filter synthesizer requires many references, which makes it extremely expensive. Using dividers (hence "mix/filter/divide", as shown in Figure 2) reduces cost because fewer references need be generated, but then phase ambiguity is introduced. Sciteq has developed a patented method by which phase memory is preserved in a mix/filter/divide design.

Indirect synthesis (Figure 3), also called "phase-lock-loop" or PLL, compares the output of a voltage controlled oscillator (VCO) with some reference signal. As the output drifts, detected errors produce correction commands to the VCO, which responds accordingly. Error detection and corrections occur in a phase detector, which adds phase noise close to the carrier, though a PLL can outperform direct synthesis at larger offsets. Fine steps degrade phase noise, and fast switching is difficult to achieve with a PLL design even with the use of aggressive VCO pretuning techniques.

Figure 3

The DDS

Direct-digital synthesis (DDS) is the most recently developed frequency synthesis technique, dating from the early 1970s. All three techniques have been available to designers for decades, but it is the direct-digital synthesizer (DDS) that is evolving the most rapidly today. In fact, only a few years ago the DDS was a phenomenon with little utility, but now it is an important design tool that can not be ignored by the architects of any system demanding frequency agility. All other signal generation techniques begin with some sort of oscillator, the output of which is manipulated or controlled by the synthesizer. The DDS is unique because it is digitally deterministic; the signal it generates is synthesized from a digital definition of the desired result.

A DDS uses logic and memory to digitally construct the desired output signal, and a data conversion device to convert it from the digital to the analog domain. Therefore, the DDS method of constructing a signal is almost entirely digital, and the precise amplitude, frequency, and phase are known and controlled at all times.

DDS Architecture

The DDS is sometimes referred to as a Numerically-Controlled Oscillator (NCO), but since no element of the DDS "oscillates" (in fact, this is one of the concept's most important features) that is a misnomer, and of the three classic techniques only the DDS truly "synthesizes" the output waveform, this document will hereafter use "DDS".

The DDS seems architecturally simple (Figure 4), yet provides persuasive advantages that are difficult or expensive to achieve with alternative synthesis methods. These advantages include very fast switching (typically submicrosecond) which is important in spread-spectrum or frequency-hopping systems, including commercial spectroscopy and automatic test equipment (ATE) systems, and no system can change frequencies as rapidly as a DDS. Additional advantages include fine steps, excellent phase noise, transient-free (phase continuous) frequency changes, extraordinary flexibility as a modulator, and small size, among others.

There are disadvantages also, of which two impose serious restrictions upon the designer. The DDS covers an operating range limited by sampling theory (Shannon, Nyquist). Practically, the output is limited to about 45% of the maximum clock rate at which the logic can be operated. The broadest bandwidth DDS yet achieved has been clocked at somewhat over 1GHz, with an output bandwidth of about 450MHz. The second limitation is spectral purity, which is governed by the density/complexity of the logic circuitry that is attainable at the desired operating speed. Spectral purity and operating bandwidth are inversely correlated, as will be shown. Despite these limitations, the DDS has evolved into an important tool, and some of its functional capabilities are not attainable with any other signal generation technique.

Though there are many variations, the conventional DDS architecture can be viewed as a simple assembly comprised of only three active components: the phase accumulator, a mapping device, and a digital-to-analog converter.

Figure 4

The phase accumulator is an arithmetic device that performs the discrete function of mathematical integration: Sn = Sn-1 + d. Two basic DDS accumulator structures exist; one manipulates binary data and the other operates with decimal values, accumulating data in binary-coded decimal (BCD) format (Sciteq patent). In application there are several variations, including the use of pipelining in high speed circuitry that can degrade the speed or update rate of the DDS. The output of the accumulator is a correlation between the commanded frequency and the clock, in the form of a phase ramp described as wïT or wïnïT; T is the sampling rate of the DDS.

The second component in a DDS is essentially memory, or a mapping device that performs the non-linear transformation of wt Þ sin(wt). This is usually done with ROM/RAM lookup tables. However, output signals of high quality require many bits to define both wt and sin(wt), thus requiring large memories.

If the output is to be over a usable bandwidth, the memory must also be fast. Since memory is the slowest digital device in the chain (logic gates operate today at 5GHz, while memory is about an order of magnitude slower), four significant approaches have emerged. The first is to multiplex N memories so that each operates at only 1/N of the system clock speed (Sciteq patent).

The second uses approximation techniques that exploit the smooth/monotonic properties of the SINE function to compress the memory by as much as 50:1 - this process (Sciteq patent pending) employs digital signal processing (DSP) disciplines. The third approach is "ROM-less" execution, with large logic arrays and small or absent memories.

The fifth approach weights the bits in the data conversion device, and while this method holds promise it has not yet been executed in usable form. Experimentation in this area is being conducted by several groups.

Digital-to-Analog Converter (DAC)

While it is possible to multiplex both logic and memory to achieve very fast (theoretically, any) clock rates, eventually it is the DAC that limits the performance of the system. The traditional DAC consists of a fast switch matrix plus a "stack" of current sources. Linearity depends upon analog (current source) error, as the accuracy of the source corresponding to the MSB must be better than the current flow of the source corresponding to the LSB. In a twelve-bit system, that is a formidable issue.

Further, the settling time of the current sources may limit the speed of the system. Overall, the DAC is unquestionably the limiting factor of the DDS. Assuming a perfect DAC, with ideal linearity, noise is still introduced by quantization errors. That is, when the ROM calls for an amplitude that falls "between" two current sources, the output waveform is degraded and spurious energy introduced.

Experimentation in DAC technology continues, with weighted DACs in the forefront. Other aggressive concepts include a laser/optical DAC, and a one-bit DAC with very heavy oversampling. The latter approach has, in fact, been implemented with interesting but not yet practical results.

Digital vs Analog Performance.

Logic alone (accumulator and ROM) can produce extremely accurate digital signals and the digital portion of the DAC can also be accurate. That is misleading, however, because theoretical digital performance is inevitably corrupted by the third active component of the DDS - the DAC. To be meaningful, DDS performance must be measured at the output of the DAC for two reasons. First, that is where the usable waveform first appears. Second, the DAC degrades the signal by 10­20dB, or even more at very high speeds. When spurious levels at the output of the ROM are "calculated" and then compared to measurements at the DAC output (in the real analog domain), the discrepancy can be large and depends upon the quality and performance of the DAC.

Any reasonably-designed DDS will provide excellent phase noise performance (typically that of the clock itself, without degradation). The "noise" generated by a DDS is therefore almost entirely discrete signals (spurs). Theory permits DDS spurious levels equal to approximately 6dB per bit of quantization in the DAC, thus an 8-bit DAC can theoretically attain ­48dBc spurs. If the remaining circuitry is designed and executed with no error whatever, and ignoring RF problems within the DAC (glitch energy, intermodulation, loading, timing, etc.), there will remain two contributors to spurs.

First is the precision with which the accumulator defines phase, and second is the quantization accuracy of the DAC. Given those two numbers, it is possible to estimate the theoretical limit of spectral purity of any given DDS, as shown in Figure 5.

Spurs are even more predictable. For instance, assume that the accumulator is controlled by some specific bit pattern of the 32 frequency bits available and outputs 14 phase bits, and the ROM maps the phase data to 12 bits of amplitude. Assume further that the DAC is not a 2's complement device and that 90° of the sinusoidal waveform is mapped (it is "flipped" and "flopped" digitally to construct all 360°). Under those circumstances, and for any clock, the dominating spurs can be predicted as to their amplitude and location (frequency).

As one possible application of this predictability, suppose the system requires generation of 100.00001MHz, but an algorithm determines that the bit pattern for that frequency will produce a -45dBc spur. If the worst spur at a commanded frequency of 100.000101MHz is at -50dBc, perhaps that frequency deviation will be acceptable.

Figure 5

In a DDS, spurious signal levels are governed by the accuracy to which the digital circuitry defines the output waveform, plus the effect of glitch energy added by the digital-to-analog converter, plus yet another category of potential problems. Typical RF issues (intermodulation, timing, loading, clock feed-through, etc.). Improved digital accuracy adds circuit complexity, hence reduces the maximum clock rate. There is therefore an inverse correlation between the two principal characteristics of the DDS: bandwidth and noise content.

Figure 6

In any signal source, signal degradation follows multiplication at a 6dB/octave rate (20 logn). This means that a DDS that covers 100MHz with -45dBc spurs can be made operationally equivalent to one that covers 50MHz with -51dBc spurs or 200MHz with ­39dBc spurs, as shown in Figure 6. While it is practical to multiply and divide the output of the DDS to achieve the desired combination of spectral purity and bandwidth, that approach is not suitable to applications where the DDS is used as a multi-mode modulator.

As an example, consider an accumulator that outputs phase with 12-bits accuracy, memory that maps those data to 10-bits for the DAC, and an 10-bit DAC. According to theory, the best spurious performance that can be achieved is -58dBc. Similarly, mapping 14-bits of phase data to 12-bits of quantization produces, at best, -72dBc spurs. The task of achieving this mapping performance is not straightforward. Classical translation techniques demand over 190k of memory, which imposes no problem at a few MHz clock rate. Achieving a combination of 190k of memory and several hundred MHz (or even 1GHz) clock rate - which corresponds to 1 nanosecond access time for nearly 200k of memory (!!) - requires some non-classical technique. Several have been developed.

Within the limitations described above, it is relatively simple to design an accumulator and memory combination that produces excellent digital performance. The best designs produce a digital signal with spurious levels of ­90dBc or better. Of course, the spurious output of the DDS must be measured after the digital to analog converter (DAC), since the DAC by itself degrades the signal more than all the circuitry that precedes it. That -90dBc digital spurious performance is subject to intermodulation, timing, clock feedthrough, loading, and other common RF problems that are aggravated by higher clock rates. The greatest signal corruption is produced by the fundamental operation of the DAC itself.

In the DAC, quantization error swamps earlier contributors to spurious energy in the DDS output. Assuming a perfect DAC design, quantization error limits spurious suppression to 6dB per bit of resolution, so an 8-bit DAC is capable of -48dBc spurious performance, a 12-bit unit can do -72dBc, etc. Because those limits are so severe in comparison, it is meaningless to consider the digital spurious performance of any competently designed logic that precedes the DAC.

Another issue in the DAC is glitch energy, or extraneous signals produced during the transitions of the conversion process (Figure 7). Such energy is introduced by the switch matrix as it turns the current sources ON and OFF.

Figure 7

As can be seen, when the DAC is operated at high clock rates the glitch takes the same time to settle but the overall step is reduced in the time domain, so there is a corresponding reduction of the percentage of each step that is linear, and a corresponding increase in the percentage that contributes to spurious energy. It is only that linear portion that is useful.

This problem can be addressed by a switch that closes to pass the signal only after the DAC has settled to its new level. Most switch designs introduce extraneous energy of their own, though Sciteq (among others) has designed a switch that introduces no glitch energy. The basics are shown as Figure 8.

Figure 8

DDS switching characteristics

The manner in which a DDS digitally constructs its output means that precise and fast manipulation of the digitized data is easy and economical. Switching mode and speed are parameters of increasing importance to the system designer: first, consider mode.

A DDS changes frequency in a unique manner when compared to oscillator-based synthesizers. Changes are without significant extraneous transition energy, because a commanded frequency change simply sets a new amplitude of the "next" bit addressed by the DAC; in Figure 9, the "next" amplitude designated at the "next" clock tick, would comply with the new frequency.

Figure 9

Frequency changes look like those of a VCO - smooth and without phase discontinuity, as shown in Figure 10. Because of this capability, only the DDS can synthesize a simulated Doppler signal, or synthesize linear FM.

Figure 10

As shown in Figure 11, DDS frequency changes occur smoothly as the ramp generated by the accumulator changes. Combining that smooth transition with fast switching means that a DDS can operate very much like a synthesized VCO, sweeping across a range with synthesizer accuracy but without the glitches and transients produced by any other synthesizer technique. When the signal is in the digital domain it is economical and easy to manipulate it, and the result is a precision not available by analog means.

Of the synthesis techniques, this characteristic is unique to the DDS, and enables it to produce a synthesized "chirp". It is also important in EW applications, where generation of undesired signals during frequency changes may demand complex blanking circuitry.

Figure 11

Switching speed is an issue in many synthesizer designs, but before it can be judged some standard must be established, as in Figure 12.

A synthesizer was once considered "fast" when it could settle at a new commanded frequency within a few milliseconds. Evolution of direct-analog synthesizers allowed the designer to achieve settling within a few microseconds. When compared by a strict standard (see Figure 4), the DDS is unquestionably the fastest switching technique. The slowest designs include pipelining (a timing technique used by the IC designer) which degrades switching performance of some highly complex designs. When switching speed (read "update rate" in a chirp generator or LFM system) is a critical issue, DDS speed can be as fast as one clock cycle plus the delay added by the output filter. Some DDS designs can switch across any portion of their full bandwidth in one clock cycle, which means that a synthesized LFM system -- based upon a DDS -- can update at rates as fast as 1GHz.

Figure 12

Fast switching is required by a variety of applications. Spread-spectrum and frequency-hopping systems by definition require fast switching. In EW, ultra-fast switching permits a single signal source to handle many different assignments. There are also many non-military applications that demand speed, including nuclear magnetic resonance spectroscopy and imaging, and test instrumentation. As one example of the latter, there are cases where ATE throughput is determined by the agility of a signal source, hence improved switching speed reduces the number of required systems.

Fine frequency steps are easy to achieve with a DDS because relatively small increases in circuit complexity can add decades of additional resolution. Most of today's DDS designs support step sizes finer than one Hertz, and many can achieve one milliHertz or better. While high resolution (fine steps) requires additional echelons of mix/filter/divide synthesizers, or higher division ratios in indirect synthesizers with corresponding degradation of phase noise performance, it is virtually without penalty in the DDS.

It is important to avoid confusion between "switching speed" and "update rate". Switching speed, as defined above, is the time between strobing a new frequency command and the output settling at that new frequency. "Update rate" is the rate at which the commanded frequency can change rather than the delay between cause and effect. When pipelining is a factor, the two are not the same.

Modulation and Complex Waveform Generation

Systems that transmit, receive, and/or process intelligence require some form of modulation, which is the deliberate distortion of a carrier to impress intelligence (data) upon it, in a manner that permits the subsequent recovery of that information. Any signal - including a complex waveform - can be completely defined by only three parameters: A(t) for amplitude, fw(t) for frequency, and f(t) for phase. Modulation requires manipulation of one or more of those parameters, which is ordinarily achieved by adding circuitry to a basic RF source (whether it is a simple crystal or a frequency synthesizer).

The DDS is an optimum modulator because waveform manipulation is simple and inexpensive while the signal is in the digital domain. The addition of a few parts to the DDS will support aggressive combinations of frequency, phase, and amplitude modulation. With DDS technology, minor modifications of the basic architecture will support virtually all modulation schemes because the DDS can impress the required modulation directly upon the carrier as an integrated part of the digital construction of the output waveform, without the need for a separate modulation subsystem.

As shown in Figure 13, FM is achieved before the phase accumulator; phase is modulated before the memory; amplitude is modulated by an input between the memory (ROM) and the digital to analog converter (DAC). A varying analog voltage applied to the DAC will also permit control of amplitude. When a DDS is constructed with such control over the signal, it can be used as a generator of complex waveforms.

Figure 13

Frequency modulation (FM) is achieved by digitizing the information and then adding the digital result to the command word appearing at the control port of the phase accumulator, as shown in Figure 14.

Figure 14

The combination of fast switching and glitch-free transitions make the DDS an optimum frequency-shift keying (FSK) modulator. FSK can be achieved with a DDS by registering two frequencies in two registers, and allowing the modulation data to toggle between them (a function provided by Sciteq's DDS-1).

Minimum-shift keying (MSK) is an FSK-derivative used in many classes of systems because of low sidelobes, and a DDS is the only theoretically perfect MSK modulator. Other approaches to MSK produce glitch energy at transition points, which reduces the effectiveness of the technique and complicates system design.

Quadrature (QPSK) or more complex M-ary FSK appears in some communication systems, and fast-hopping M-ary FSK is used extensively in anti-jam communications and also in industrial situations where interference is generated by environmental conditions.

For a special sub-set of frequency modulation, linear FM, or linear FM Chirp, the DDS has shown itself to be a viable alternative to the existing (and limited) techniques used in the past such as voltage swept VCO's and fixed SAW devices. FM chirp modulation is used in advanced radar, anti-jam electronic warfare, and similar system architectures. Chirp signals have been traditionally complex to generate. VCOs have problems in linearity and total accuracy. Such systems had to be linearized as well as kept at constant temperature and continuously calibrated. This makes the hardware complex and expensive. Linear FM is much more complex to generate in the analog domain.

Chirp update rate is a challenge of increasing importance to many programs. Several segments of the RF industry wish to rapidly implement waveform changes commanded by the system controller. This issue is critical to certain new-technology radar systems, where optimum linear FM performance demands a synthesized signal, but with update rates not achievable from conventional DDS architectures.

One current Sciteq program is developing a DDS-based chirp generator with an update rate of 100MHz, and architectures are achievable which will support update rates equal to the reference clock. Such aggressive designs require substantial deviation from classical DDS architecture, and considerable innovation is required in their implementation. For more information on the use of a DDS as a linear FM, or chirp modulator, call Sciteq and request an application note.

Phase modulation (PM, or fM) is used extensively in satcom, telecommunication, and communications. BPSK, QPSK, 8-ary and 16-ary phase shifting are frequently encountered. Very high speed BPSK is used in spread spectrum communications for anti-jam benefits, and is a useful technique for overcoming interference in hostile industrial environments. It is also being considered for cellular telephony, for similar reasons. In radar, BPSK is used for pulse compression (using Barker Codes) or poly-phase codes for much longer sequences. A DDS supports such phase modulation with accuracy/performance not otherwise attainable, as shown in Figure 15.

Figure 15

A DDS can shift the phase of the output signal if an adder is placed between the accumulator and the ROM to shift addresses in accordance with the data appearing at that adder as shown in Figure 16. It is possible to achieve nearly any number of phase levels using this technique, and the accuracy will be far better than is possible with analog methods. Excellent analog phase modulators achieve 2° or 3° accuracy; the first phase-control DDS (a Sciteq product) achieved 1.4°, and current designs are able to achieve almost any level. As an example, Sciteq's DDS-1 has 16 bits of phase control available, which can meet virtually any modulation requirement. 16 bits may be barely sufficient in some aggressive LFM implementations, where it becomes critical to phase-match two signals. Nevertheless, for many system requirements, the ability of the DDS to precisely control phase is an important attribute that cannot be duplicated by any other means.

Figure 16

An adder between the accumulator and the ROM will define phase with an exactitude limited only by the number of bits in the adder. BPSK and QPSK are simple, of course, and an 8­bit adder achieves 256 discrete phase levels (~1.4° steps), etc. Such information density is practical only with a DDS.

Figure 17

Amplitude modulation (AM) is ordinarily implemented by a multiplier between the memory and the DAC (Figure 17), but technology does not yet support multipliers with the speed and circuit density required by GaAs DDSs today. At least one other fundamentally different transformation technique is available to avoid the use of a multiplier, however, as implemented in the Sciteq DDS-1 (Waveformer), which provides 11 bits of dynamic amplitude control/modulation. Also, with some DACs it is possible to provide reasonably accurate analog amplitude control by varying a control voltage.

Pulse modulation is supported by a DDS's ability to execute a high-isolation MUTE function with one digital control bit at the DAC registers. This technique allows preservation of phase coherence from pulse to pulse. A second option is to use a RESET function (one bit, but applied at the accumulator), that permits signal resumption at a known point in phase. In both cases, the ON/OFF ratio will be much better than 100dB. It is possible to include both MUTE and RESET in one waveform generator design.

Additional logic increases power consumption and complexity, but improvements in device design and basic semiconductor technologies (advanced digital Si and GaAs) support even very aggressive modulation scenarios.

Complex waveform generation combines frequency synthesis with modulation, usually by the techniques described above. When more than one system radiates from a given platform, the sum of the signals can be defined by the three parameters described above. Whether communications, radar, electronic warfare, navigation, or even a radar altimeter, the output of more than one platform system can be summed as one complex waveform. When using a DDS, this can be an integrated process because all these parameters are simultaneously manipulated while the signal is digitally constructed.

Figure 18

Another technique involves memory. By changing the ROM to RAM in the DDS as shown in Figure 18, virtually any desired waveform can be generated. The clock may be fixed or variable; in the latter case, the output waveform can be defined with greater latitude. In effect, the DDS operates like an arbitrary waveform generator (ARB).

Choosing and Using a DDS

The DDS uses fundamentally simple architecture, but successful execution demands a unique combination of digital, analog, and general design skills. A combination of good spectral purity and high operating clock rates (thus broad bandwidth) is difficult to achieve. It is also practical to exploit the ease by which the signal can be manipulated while it is in the digital domain. Modulation, gating, and timing are all relatively easy to achieve - and significant economy results from the elimination of analog means of achieving inferior results.

The DDS is becoming a mature technology. Because it is relatively easy to do so in most applications, the DDS should be designed to include as many system functions as are practical, to reduce system cost. Additional features (i.e. an adder to inject phase shift data) can increase die complexity and risk, particularly when speed is to be maximized. Only when yield problems increase unit cost, or circuit density requirements limit operating speed, should functional compromises be accepted.

Selecting a DDS for a given application is not simple. The combination of spectral purity and bandwidth, power budget and required supplies, the overall frequency plan, and the mechanical footprint will drive the decision. Add the cost of internal engineering when anything but a turnkey solution is selected, and the decision process can become complex.

By itself, the DDS is growing more useful due to combined improvements in bandwidth and circuit density (thus spectral purity at a given bandwidth), plus the relative ease by which waveform control is implemented. These factors still limit utility, however, and most applications that exploit the DDS combine it with either direct or indirect circuitry.

The ability to efficiently and economically produce fine frequency steps enables the DDS to replace multiple loops in many PLL designs. The resulting PLL+DDS architecture covers its range in fine steps while retaining reasonable division ratios, thus preserving phase noise. In such cases, there is no reason to accept the cost and complexity of multiple loop synthesizers when similar performance can be achieved by adding a DDS.

In combination with a PLL, the DDS need not cover more than a few MHz, because any competent PLL design can cover its operating range in steps of one or two MHz, and the DDS will only "fill in the gaps" with fine steps (Figure 19). The insertion of a DDS into a PLL is the most common application of DDS technology, and the market offers a variety of low-cost DDS products to do this job. The result will cover the overall operating range with reasonable phase noise, good spurious performance, and fine steps. This technique is suitable to all applications where switching speed is not a factor (though pretuning can achieve better but seldom submicrosecond switching), and where phase noise is not critical (direct designs are inherently better than PLL at some offsets from the carrier).

Figure 19

There are several fundamental techniques by which a DDS can be combined with a PLL. In simple applications where only multiplication is sought (and spectral purity is noncritical), the output of the DDS can be injected directly into the phase comparator. When spectral purity is important, a combining loop can be used. Even with two loops, the resulting circuitry is much simpler than would be required with an all-PLL approach to the same combination of phase noise and step size.

Another approach that exploits the DDS is upconversion, or integration with a mix/filter/divide (direct-analog) synthesizer, as shown in Figure 20. This technique permits 60-70% of the DDS' output to be translated to a new frequency range. The limit is determined by the filter, as shown. The two sidebands must be sufficiently distant as to permit the filter to select one of them.

The basic direct-analog synthesizer consists of "echelons" of mix/filter/divide modules. In addition to basic design tasks, achieving higher operating frequencies requires higher available reference frequencies. Finer steps, however, demand more and more modules of mix/filter/divide circuitry until overall complexity becomes a problem. That problem can be alleviated by using a DDS to cover the fine steps, in a manner similar to that used with PLL circuitry. The result preserves the essential advantages of the direct-analog design (excellent phase noise, fast switching) and only the spurious performance of the DDS remains an issue - but that can be resolved by dividing, or by using a DDS design with sufficient performance. There are many innovative techniques by which principles of direct (mix/filter) synthesis can exploit the advantages of the DDS.

Figure 20

Figure 21


More aggressive mix/filter+DDS combinations have been built, including the successful design shown in Figure 21. This design was originally executed in silicon, but in GaAs - using existing capabilities - it can be built to cover over 1GHz in output bandwidth while preserving the spectral purity of the underlying basic DDS.

DDS Evolution

The most obvious "trade-offs" in a DDS are speed (BW) and spectral purity. The more dense the circuitry the more accurately the output waveform will be defined, and the better the spurs will be suppressed - but additional circuitry limits speed, hence BW, etc. Other factors are often important, including modulation functions, switching speed or chirp rate (pipelining), etc. There is no longer one DDS aspirin for all system headaches. In fact, the technology has grown so complex and diverse that there are some DDS capabilities that are mutually exclusive.

Today's DDS products are available at several levels of integration. DDS capabilities are available as an instrument, a card for the IBM-PC, a complete subsystem in a module, on a board, or in a hybrid, while others are sold only as chips or chip sets, to be integrated by the user and added to the system.

In the rapidly growing DDS business there is no single "state of the art". There are highly optimized modulators, designs tailored specifically for integration with PLL synthesis circuitry, others with extraordinarily fine steps, still more with up to 32-bits of phase control, products offering bandwidth at any cost, and many more variations that could claim to be state of their particular art. Most designers agree that improvements in the combination of bandwidth and spectral purity generally make the technique more useful, but that is not sole the criterion by which a given DDS can be judged.

Of standard products offered commercially, the broadest bandwidth is achieved by Sciteq's ADS series, which covers over 300MHz with -40dBc spurs (that equates to about 37MHz bandwidth with -58dBc spurs). Sciteq has developed a hybrid version of that architecture which in prototype form has already covered over 400MHz BW.

As indicated in Figure 22, the DDS industry has separated, diverging in directions that are mutually exclusive because bandwidth and spectral purity are inversely related, and bandwidth and power consumption are directly related. The DDS market is therefore divided by functionality, speed, and ñ above all ñ price. Enhanced functionality generally means more circuitry, hence more power consumption, larger die size, more control pins, and greater cost.

Figure 22

Broadband DDS designs are useful in a variety of applications ranging from instrumentation in ATE to spread spectrum telecommunications and electronic warfare. In the last case, certain existing aggressive designs require over 200MHz BW, and the DDS is used as a combination modulator and signal source. Typically, the DDS is upconverted by translation (simple multiplication corrupts spectral purity) and then, using multiple LOs and switched filters, is spread across the required operating range. Often, the more bandwidth from the DDS, the simpler the rest of the system.

The "commodity" DDS is used by the hundreds of thousands in many ways, both directly and as a building block of a more complex design. Sciteq does not work in the commodity DDS market. Such narrowband DDS products, usually executed in low-power CMOS and built at low unit cost, are available to cover as much as 30MHz while providing extensive signal manipulation capabilities. When used to improve the phase noise of a PLL synthesizer, or to reduce circuit complexity of a direct-analog design, these are usually the DDS products of choice. Perhaps the most all-inclusive narrowband DDS offered today is Sciteq's DDS­1, a one square inch device that includes the DAC. Spurs are better than ­60dBc, and the design includes phase, frequency, and digital amplitude modulation. Two registers are provided so FSK/MSK is also simple to implement. A block diagram that defines the functional characteristics of the DDS-1 is shown as Figure 23.

Figure 23

In addition to universality and bandwidth, another set of decision-drivers involves form factor and packaging. Aggressive DDS designs might be built into a fan-cooled chassis for lab-benign environmentals, in modules, or as 883-screened hybrids built to 1772 standards. A complete DDS can also be built as a monolithic part, with serial programming to support inexpensive, low pin count, packages. The criteria by which the final packaging selection is made might include cost, bandwidth (and its affect upon the architecture of the rest of the system), modulation, spectral purity, and power dissipation. In a DDS, fine steps, small size, digital reliability and excellent phase noise are usually assumed.

Over the next few years, the DDS will evolve in two directions that will continue to diverge (Figure 22). The first will be characterized by very low cost and a max clock rate near 50MHz, plus good spectral purity, for integration into PLL and some mix/filter synthesizers. This design will likely be sold even at the hobbyist level.

The second is represented by a family of aggressive broadband DDS designs, initially for government/military applications, now a major design effort at Sciteq. Executed in advanced silicon or GaAs, these advanced designs are suited to the requirements of demanding system architectures.

Obviously, it is only the obstacles of price, bandwidth, and spectral purity of the DDS that keep it from replacing direct-analog and PLL synthesizer programs, but today's "low-cost" designs were extremely aggressive only a few years ago. As Figure 24 indicates, the trend continues, and the goals of today's most aggressive programs will likely be attained by "low-cost" designs of tomorrow. The DDS is replacing a growing percentage of the total signal generator budget of the industry, and this trend will accelerate.

Figure 24

Developing Advanced Broad-bandwidth DDSs

In the advanced DDS market, the combination of speed and spectral purity differentiates products. Spectral purity is related to circuit complexity, particularly in the DAC. While it is theoretically possible to multiplex both the phase accumulator and the memory to almost any level (a Sciteq patent), and therefore to achieve virtually any speed, the DAC is a bottleneck through which the signal must pass, and it is DAC technology that imposes the limit on the advanced DDS. Many designers have believed that the primary challenge with DACs is quantization, but that is only one problem.

The accumulator is the least critical of the DDS building blocks. Though it must be executed carefully to ensure inclusion of required functionality (phase control, gating, etc.), the accumulator is not a serious problem in expanding the performance of advanced DDSs. In fact, a new Sciteq accumulator concept reduces complexity, gate count, die size, and power well below conventional architectures, further reducing risk and enhancing the practicality of ultrafast monolithic DDSs.

A far more daunting issue is the memory used to convert phase data to amplitude data. Conventional methodologies require approximately 192k to map 14 bits of phase information (from the accumulator) to 12 bits of amplitude (for the DAC). No current technology supports a ~200k memory at high speed (500 MHz or more), but Sciteq has developed a nonconventional approach that shrinks memory considerably.

Figure 25

Based upon a Taylor expansion series approach that exploits the monotonicity of most of the sinusoidal waveform (Figure 25), Sciteq's patent-pending memory technique shrinks the required ROM from 192k to ~3k, which is practical at two nanoseconds. This technique is exploited in Sciteq's custom GaAs ASIC used in the ADS-632, for instance.

The result of the ADS-632 problem is impressive. Convinced that historical information on DDSs is potentially inaccurate because specifications were generated using insufficient data, Sciteq has developed a new technique for evaluating DDS performance. As shown, when the ADS-632 is clocked at 500 MHz, signals up to one-fourth the clock (125 MHz) can be produced with an absolute worst-case spur level better than -60 dBc.

Instrumentation

The preceding discussion concerns OEM applications for DDS technology, which excludes an important and growing DDS market segment: instrumentation. Various instruments have exploited a DDS during the past decade, with varying degrees of success.

In some, the DDS is the sole signal generation circuit. In others the DDS is used to augment or simplify either a PLL or a mix/filter/divide circuit.

Two new generations of DDS instrumentation are now emerging. One uses a DDS as the basic signal generator, usually built as one or more ASICs, plus intelligence. DDSs have been built in VME, Cambion, and other standard board formats, and work is now being done on products for the new VXI market. Sciteq's MultiGen is a patented DDS built on a PC-bus card, which combines the intelligence of the host computer with an onboard 68000 microprocessor to produce an extremely powerful virtual instrument. In industrial computers and lab applications, VME and PC-bus DDS products are becoming more and more useful because they exploit the underlying computer.

The most aggressive instrumentation application contemplated for new DDS designs will be an instrument based on the new wideband DDS (developed primarily for the OEM market). By 1991, when the DDS can be cost-effectively built to cover >400MHz with <­60dBc spurs, perhaps on two or three square inches of hybrid substrate, it will take little to build an interface, display, keyboard, and power supply into a small chassis. Such an instrument will be very powerful, with elaborate modulation capabilities and fast switching. In fact, there are no other approaches that permit broadband synthesized "chirp" and sweep functions, Doppler simulation, or EW signal emulation. Overall, the market for DDS-based instruments is viewed as good and growing.

The DDS is evolving rapidly to maturity. In OEM applications the DDS technique solves many problems, and it appears in a variety of systems. Combined with PLL or direct-analog circuitry, the advantages of the DDS can be translated to any required point in the spectrum. DDS-based instrumentation is now on the market, and much more will soon be developed. In fact, it appears that within the next few years there will be few if any instrument synthesizers designed without a DDS contributing the cost-effectiveness of the result.

Exploiting the DDS is now a low-risk project, and the technique has grown from an engineering novelty to a serious engineering resource that conveys a competitive advantage to the system that employs it. In fact, the proliferation of cost-effective DDS­based systems indicates that systems that employ only analog signal generation suffer competitively.

===================================

DDS Selection

A program manager's guide to the DDS - support for selection decisions...

A Resource.

The Direct-Digital Synthesizer (DDS) has evolved into a supreme resource for the system architect, and for the "synthesizer designer," as well. Though the technique was regarded as a novelty only a decade ago, it now is a fundamental building block in many categories of systems.

DDS Categories.

Current DDSs fall into two classes: high performance and commodity, though the line dividing them is moving steadily with evolution of the technologies on which they depend. In 1985 a "high performance" DDS could be clocked at 50 MHz using 100k ECL logic, and the DAC was an 8-bit part so spurious performance was about -45dBc. Today, monolithic CMOS DDSs operate even faster, and with enhanced functionality and improved quantization. The 100k ECL design of a decade ago cost about $3,000, while its CMOS counterpart today is about one-hundredth of that price. The DDS business has never stopped changing.

Speed is the primary differentiating factor between low cost and advanced DDSs. In either case, a DDS can add functionality and economy to the system, because it does certain things that no other synthesizer technique can do.

The Commodity DDS.

Today, the "commodity" DDS costs under $100, but the functionality and performance available at that price is steadily growing. Further, DDS products at this level are easy to integrate and require few special skills.

A "commodity" DDS ñ by itself ñ will meet the requirement of some systems. For instance, HF radio is generally defined as the band from 2-30 MHz, so ELF, VLF, and HF can all be tuned with a relatively inexpensive DDS.

In vibration-testing or ultrasound systems (cleaning or non-destructive testing, for instances), the upper frequency range requirement is within the limit of a cost-effective DDS. The remarkable deterministic nature of a DDS permits the designer to create very precise waveforms that optimize the system result and achieve performance not possible with other signal generation techniques. Most DDSs change frequencies without any period of ambiguity during the transition, so ultrasound systems can be designed without concern that uncommanded frequencies will corrupt performance. Vibration testers are even easier to build (due to mechanical inertia), but the nature of the DDS permits the construction of waveforms and vibration profiles that closely mimic the environment in which the unit-under-test will be operated.

The commodity DDS is more often used as a building block of complex PLL and direct-analog synthesizers. Various PLL+DDS architectures have been used successfully. The easiest approach is to simply pass the DDS' output through a filter and make the result a reference to the phase detector. That technique has been used by Sciteq since 1984, but the loop multiplies spurs from the DDS, making close-in spurs unacceptable to some systems. Another 1984 Sciteq solution is to use two loops; one covers the desired output range in coarse steps, the second combines the DDS with the first loop to achieve fine steps. A third Sciteq approach (recent) has been very successful; it uses an SSB modulator to combine the output of the DDS with the output from the VCO, generating a fine-step signal to the PLL.

Such a DDS can also be used to improve the step size of direct-analog synthesizers. In such cases, conventional mix-filter circuitry is used to attain the required operating range, and the DDS' input is introduced at a strategic point where it can (usually) be divided to improve spurious performance before further conversion and bandspreading.

A "commodity" DDS permits a PLL synthesizer to reduce step size with better spectral purity than is achievable by simply increasing division ratios. It performs a similar function when married with direct-analog circuitry, as smaller steps can be achieved without the usual number of modules.

The High Speed DDS.

The "advanced" DDS may cost $5,000 or more, and this product category is also growing in performance. Integrating a DDS that clocks at more than 500 MHz is a job that often requires serious RF understanding.

By definition, an "advanced technology" DDS is fast; it uses GaAs or high-speed silicon semiconductors to achieve broad bandwidth. Such designs dissipate considerable power, hence require serious consideration of the thermal gradient to the environment. As of mid-1994, such designs can operate from DC to about 400 MHz, though there are some evolving products that cover an even broader frequency range. In fact, at least one experimental design generates 1000 MHz bandwidth, by constructing frequencies from minus 500 MHz to positive 500 MHz. Though few engineers think about positive and negative frequencies, the nature of a DDS permits phase to rotate in either direction.

In addition to bandwidth, this category of DDS provides very fast switching, but definitions must be considered when making comparisons. If "switching speed" is the period between a command to change frequency and stability at the new frequency, then system latency must be considered and the figure might be tens of nanoseconds. If "settling time" is the period of ambiguity between departure from the first frequency and stability at the new one, then the DDS might be seen as an order of magnitude faster.

When "update rate" is the issue, it is determined by that period after a new frequency command before a new one can be accepted, and that depends upon pipelining and latency also.

In short, switching speed across a broad band is often the single most important consideration in selection an "advanced" DDS. Unless the terminology is carefully defined, however, a performance specification might be very misleading.

Influencing DDS Decisions.

The first issue is bandwidth. If one plans to use the DDS by itself, then one must already have that information and know whether the requirement can be met with a "commodity" DDS. If one plans to integrate the DDS with either PLL or mix-filter circuitry, then one should develop the frequency plan in concert with the DDS selection process. The system designer must understand that as DDS bandwidth goes up, so does cost of the DDS ñ but, in many cases the cost of the remainder of the system will fall. It's the designer's responsibility to reach the most cost-effective set of trade-offs.

The second issue is usually the levels of spurious signals (uncommanded periodicities) in the output. Many DDSs can achieve -50 dBc or better, but -60 is difficult, particularly over a broad (>50 MHz) bandwidth. One source of the problem is the DDS specification; the term "typical" indicates performance at "most" output frequencies. "Worst-case," or "guaranteed," means the highest spur generated at any freqëncy of which the unit is capable. In any DDS there are certain bit patterns (perhaps as few as one one-hundredths of a percent) where the spurious signal levels are far worse than others. Such spurs are due to a variety of causes that happen to sum at those frequencies. The difference between "typical" and "guaranteed" can become costly, even to the point where the cost-effectiveness (marketability) of the system is jeopardized.

A second "spur" problem is the system specification, which is often written based upon the performance of the instruments used in developing the system. That is, if an HP instrument has -60 dBc spurs, and works in the system, then that number may become the default specification for production, even if the system can meet the market need with much worse synthesizer performance. Insisting on the same figures as were used in development can become an expensive mistake. At some point in the design chain someone must calculate the actual requirement, and then specify it in the system.

Size and Packaging.

DDSs are small; in fact, several (in each category) have been integrated as one chip that requires only a filter to generate the desired signal. The logic is so compact that packaging is seldom a problem.

Heat sometimes is. High performance DDSs often require special engineering consideration of the thermal gradient from the semiconductor junction to the environment.

Interface.

Most DDSs use binary arithmetic, so a binary clock (i.e. 224) is required if the output is to be covered in decimal steps. Such logic produces decimal steps (i.e. 1.000 Hz) from a binary clock, or binary steps from a decimal (i.e. 10.00 MHz) clock. Sciteq has patented an architecture that uses binary-coded decimal (BCD) arithmetic, and therefore generates an output in decimal steps from a decimal output.

Another issue is serial vs. parallel. A significant portion of the cost of a commodity DDS is the package, and that cost is minimized by using fewer pins, possible only when a serial data stream controls the unit. That's slow, however.

When ultrafast switching is required, as us usually true when a broad bandwidth advanced technology DDS is used, then parallel control is the standard. Most such DDSs include registration at the input to facilitate the control interface.

Output Power.

As can be seen in the tutorial, the output power from a DDS is that of the DAC, attenuated by the anti-aliasing filter to produce a result in the -3 dBm range. In most cases the DDS must drive a mixer and therefore requires an amplifier. Amplifiers ordinarily degrade harmonics, however, so must be selected carefully. Further, in a broadband DDS, heat is already a problem that can be aggravated by the addition of a high performance amplifier.


Since 1983, Sciteq has been committed to the evolution of DDS technology, and to the development of DDS+PLL and DDS+mix/filter products that improve the competitive posture of systems that exploit them. At every level of subsystem integration, Sciteq offers a complete menu that includes all frequency synthesizer technologies.