top Project Status (03/03/2017 - 11:47:58)
Project File: | picoblaze.xise | Parser Errors: | No Errors
Module Name: | top | Implementation State: | Programming File Generated
Target Device: | xc3s500e-5fg320 |

- Errors:

No Errors
Product Version: | ISE 14.7 |

- Warnings:

349 Warnings (2 new)
Design Goal: | Balanced |

- Routing Results:

All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) |

- Timing Constraints:

All Constraints Met
Environment: | System Settings |

- Final Timing Score:

0 (Timing Report)

Device Utilization Summary | [-]
Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Flip Flops | 84 | 9,312 | 1% |
Number of 4 input LUTs | 169 | 9,312 | 1% |
Number of occupied Slices | 94 | 4,656 | 2% |
Number of Slices containing only related logic | 94 | 94 | 100% |
Number of Slices containing unrelated logic | 0 | 94 | 0% |
Total Number of 4 input LUTs | 171 | 9,312 | 1% |
Number used as logic | 101 |  |  |
Number used as a route-thru | 2 |  |  |
Number used for Dual Port RAMs | 16 |  |  |
Number used for 32x1 RAMs | 52 |  |  |
Number of bonded IOBs | 18 | 232 | 7% |
Number of RAMB16s | 1 | 20 | 5% |
Number of BUFGMUXs | 1 | 24 | 4% |
Average Fanout of Non-Clock Nets | 3.75 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Fri Mar 3 11:47:09 2017 | 0 | 347 Warnings (0 new) | 0
Translation Report | Current | Fri Mar 3 11:47:15 2017 | 0 | 2 Warnings (2 new) | 0
Map Report | Current | Fri Mar 3 11:47:21 2017 | 0 | 0 | 2 Infos (2 new)
Place and Route Report | Current | Fri Mar 3 11:47:34 2017 | 0 | 0 | 2 Infos (2 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | Fri Mar 3 11:47:37 2017 | 0 | 0 | 6 Infos (6 new)
Bitgen Report | Current | Fri Mar 3 11:47:43 2017 | 0 | 0 | 0

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | Fri Mar 3 11:35:24 2017
WebTalk Report | Current | Fri Mar 3 11:47:43 2017
WebTalk Log File | Current | Fri Mar 3 11:47:57 2017

Date Generated: 03/03/2017 - 11:47:58