`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   11:19:08 03/03/2017
// Design Name:   top
// Module Name:   C:/Users/EMRAH/Desktop/pico/ise/picoblaze/test_pico.v
// Project Name:  picoblaze
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: top
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_pico;

	// Inputs
	reg [7:0] sw;
	reg reset;
	reg clk;

	// Outputs
	wire [7:0] leds;

	// Instantiate the Unit Under Test (UUT)
	top uut (
		.sw(sw), 
		.reset(reset), 
		.leds(leds), 
		.clk(clk)
	);
	always
	begin
		#10;
		clk=~clk;
	end
	
	initial begin
		// Initialize Inputs
		sw = 0;
		reset = 0;
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;
      sw=8'hAA;
		#40;
		sw=8'h55;
		#110;
		sw=8'hAA;
		#20;
		sw=8'h66;
		// Add stimulus here

	end
      
endmodule

