### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.

Software Version and Target Device
Product Version: | ISE:14.7 (WebPack) - P.20131013 | Target Family: | Spartan3E
OS Platform: | NT64 | Target Device: | xc3s500e
Project ID (random number) | 2099b96b61fa4547b60800602b4c352d.8CF5C57157374EE4BA1DEE9D3BC9694D.1 | Target Package: | fg320
Registration ID | __0_0_0 | Target Speed: | -5
Date Generated | 2017-03-03T11:47:43 | Tool Flow | ISE

User Environment
OS Name | Microsoft Windows 7 , 64-bit | OS Release | Service Pack 1 (build 7601)
CPU Name | Intel(R) Core(TM) i7-3635QM CPU @ 2.40GHz | CPU Speed | 2394 MHz

Device Usage Statistics
Macro Statistics | Miscellaneous Statistics | Net Statistics | Site Usage
Registers=92

- Flip-Flops=92

MiscellaneousStatistics

- AGG_BONDED_IO=18
- AGG_IO=18
- AGG_SLICE=94
- NUM_4_INPUT_LUT=171
- NUM_BONDED_IBUF=10
- NUM_BONDED_IOB=8
- NUM_BUFGMUX=1
- NUM_CYMUX=38
- NUM_DP_RAM=16
- NUM_LUT_RT=2
- NUM_RAM32=52
- NUM_RAMB16=1
- NUM_SLICEL=60
- NUM_SLICEM=34
- NUM_SLICE_FF=84
- NUM_XOR=37

NetStatistics

- NumNets_Active=242
- NumNets_Gnd=1
- NumNets_Vcc=1
- NumNodesOfType_Active_BRAMADDR=10
- NumNodesOfType_Active_BRAMDUMMY=18
- NumNodesOfType_Active_CLKPIN=73
- NumNodesOfType_Active_CNTRLPIN=71
- NumNodesOfType_Active_DOUBLE=483
- NumNodesOfType_Active_DUMMY=595
- NumNodesOfType_Active_DUMMYBANK=4
- NumNodesOfType_Active_DUMMYESC=10
- NumNodesOfType_Active_GLOBAL=20
- NumNodesOfType_Active_HFULLHEX=2
- NumNodesOfType_Active_HUNIHEX=20
- NumNodesOfType_Active_INPUT=768
- NumNodesOfType_Active_IOBOUTPUT=10
- NumNodesOfType_Active_OMUX=222
- NumNodesOfType_Active_OUTPUT=196
- NumNodesOfType_Active_PREBXBY=166
- NumNodesOfType_Active_VFULLHEX=17
- NumNodesOfType_Active_VLONG=2
- NumNodesOfType_Active_VUNIHEX=37
- NumNodesOfType_Vcc_BRAMDUMMY=1
- NumNodesOfType_Vcc_CNTRLPIN=1
- NumNodesOfType_Vcc_INPUT=4
- NumNodesOfType_Vcc_PREBXBY=3
- NumNodesOfType_Vcc_VCCOUT=5

SiteStatistics

- IBUF-DIFFMI=1
- IOB-DIFFM=2
- IOB-DIFFS=2
- SLICEL-SLICEM=15

SiteSummary

- BUFGMUX=1
- BUFGMUX_GCLKMUX=1
- BUFGMUX_GCLK_BUFFER=1
- IBUF=10
- IBUF_INBUF=10
- IBUF_PAD=10
- IOB=8
- IOB_OUTBUF=8
- IOB_PAD=8
- RAMB16=1
- RAMB16_RAMB16=1
- RAMB16_RAMB16A=1
- SLICEL=60
- SLICEL_CYMUXF=22
- SLICEL_CYMUXG=16
- SLICEL_F=51
- SLICEL_F5MUX=9
- SLICEL_FFX=29
- SLICEL_FFY=29
- SLICEL_G=52
- SLICEL_GNDF=14
- SLICEL_GNDG=9
- SLICEL_XORF=17
- SLICEL_XORG=20
- SLICEM=34
- SLICEM_BYINVOUTUSED=8
- SLICEM_BYOUTUSED=8
- SLICEM_DIGUSED=8
- SLICEM_F=34
- SLICEM_F5MUX=26
- SLICEM_F6MUX=8
- SLICEM_FFX=10
- SLICEM_FFY=16
- SLICEM_G=34
- SLICEM_WSGEN=34

Configuration Data
BUFGMUX

- S=[S_INV:1] [S:0]

BUFGMUX_GCLKMUX

- DISABLE_ATTR=[LOW:1]
- S=[S_INV:1] [S:0]

IBUF_PAD

- IOATTRBOX=[LVCMOS25:10]

IOB

- O1=[O1_INV:0] [O1:8]

IOB_OUTBUF

- IN=[IN_INV:0] [IN:8]

IOB_PAD

- DRIVEATTRBOX=[12:8]
- IOATTRBOX=[LVCMOS25:8]
- SLEW=[SLOW:8]

RAMB16

- CLKA=[CLKA_INV:0] [CLKA:1]
- ENA=[ENA_INV:0] [ENA:1]
- SSRA=[SSRA_INV:0] [SSRA:1]
- WEA=[WEA:1] [WEA_INV:0]

RAMB16_RAMB16A

- CLKA=[CLKA_INV:0] [CLKA:1]
- ENA=[ENA_INV:0] [ENA:1]
- PORTA_ATTR=[1024X18:1]
- SSRA=[SSRA_INV:0] [SSRA:1]
- WEA=[WEA:1] [WEA_INV:0]
- WRITEMODEA=[WRITE_FIRST:1]

SLICEL

- BX=[BX_INV:0] [BX:20]
- BY=[BY:6] [BY_INV:1]
- CE=[CE:2] [CE_INV:5]
- CIN=[CIN_INV:0] [CIN:16]
- CLK=[CLK:38] [CLK_INV:0]
- SR=[SR:26] [SR_INV:4]

SLICEL_CYMUXF

- 0=[0:22] [0_INV:0]
- 1=[1_INV:0] [1:22]

SLICEL_CYMUXG

- 0=[0:16] [0_INV:0]

SLICEL_F5MUX

- S0=[S0:9] [S0_INV:0]

SLICEL_FFX

- CE=[CE:0] [CE_INV:5]
- CK=[CK:29] [CK_INV:0]
- D=[D:29] [D_INV:0]
- FFX_INIT_ATTR=[INIT0:29]
- FFX_SR_ATTR=[SRLOW:29]
- LATCH_OR_FF=[FF:29]
- SR=[SR:20] [SR_INV:4]
- SYNC_ATTR=[ASYNC:5] [SYNC:24]

SLICEL_FFY

- CE=[CE:2] [CE_INV:5]
- CK=[CK:29] [CK_INV:0]
- D=[D:28] [D_INV:1]
- FFY_INIT_ATTR=[INIT0:27] [INIT1:2]
- FFY_SR_ATTR=[SRLOW:27] [SRHIGH:2]
- LATCH_OR_FF=[FF:29]
- SR=[SR:17] [SR_INV:4]
- SYNC_ATTR=[ASYNC:8] [SYNC:21]

SLICEL_XORF

- 1=[1_INV:0] [1:17]

SLICEM

- ALTDIG=[ALTDIG:8] [ALTDIG_INV:0]
- BX=[BX_INV:0] [BX:26]
- BY=[BY:34] [BY_INV:0]
- CLK=[CLK:34] [CLK_INV:0]
- SR=[SR:24] [SR_INV:10]

SLICEM_BYINVOUTUSED

- 0=[0:8] [0_INV:0]

SLICEM_BYOUTUSED

- 0=[0:8] [0_INV:0]

SLICEM_DIGUSED

- 0=[0:8] [0_INV:0]

SLICEM_F

- DI=[DI:34] [DI_INV:0]
- F_ATTR=[DUAL_PORT:8]
- LUT_OR_MEM=[RAM:34]

SLICEM_F5MUX

- S0=[S0:26] [S0_INV:0]

SLICEM_F6MUX

- S0=[S0:8] [S0_INV:0]

SLICEM_FFX

- CK=[CK:10] [CK_INV:0]
- D=[D:10] [D_INV:0]
- FFX_INIT_ATTR=[INIT0:10]
- FFX_SR_ATTR=[SRLOW:10]
- LATCH_OR_FF=[FF:10]
- SYNC_ATTR=[ASYNC:10]

SLICEM_FFY

- CK=[CK:16] [CK_INV:0]
- D=[D:16] [D_INV:0]
- FFY_INIT_ATTR=[INIT0:16]
- FFY_SR_ATTR=[SRLOW:16]
- LATCH_OR_FF=[FF:16]
- SYNC_ATTR=[ASYNC:16]

SLICEM_G

- DI=[DI:34] [DI_INV:0]
- G_ATTR=[DUAL_PORT:8]
- LUT_OR_MEM=[RAM:34]

SLICEM_WSGEN

- CK=[CK:34] [CK_INV:0]
- SYNC_ATTR=[ASYNC:26]
- WE=[WE_INV:10] [WE:24]
- WE0=[WE0:26] [WE0_INV:0]

Pin Data
BUFGMUX

- I0=1
- O=1
- S=1

BUFGMUX_GCLKMUX

- I0=1
- OUT=1
- S=1

BUFGMUX_GCLK_BUFFER

- IN=1
- OUT=1

IBUF

- I=10
- PAD=10

IBUF_INBUF

- IN=10
- OUT=10

IBUF_PAD

- PAD=10

IOB

- O1=8
- PAD=8

IOB_OUTBUF

- IN=8
- OUT=8

IOB_PAD

- PAD=8

RAMB16

- ADDRA10=1
- ADDRA11=1
- ADDRA12=1
- ADDRA13=1
- ADDRA4=1
- ADDRA5=1
- ADDRA6=1
- ADDRA7=1
- ADDRA8=1
- ADDRA9=1
- CLKA=1
- DOA0=1
- DOA1=1
- DOA10=1
- DOA11=1
- DOA12=1
- DOA13=1
- DOA14=1
- DOA15=1
- DOA2=1
- DOA3=1
- DOA4=1
- DOA5=1
- DOA6=1
- DOA7=1
- DOA8=1
- DOA9=1
- DOPA0=1
- DOPA1=1
- ENA=1
- SSRA=1
- WEA=1

RAMB16_RAMB16

- ADDRA=1
- DIA=1
- DOA=1

RAMB16_RAMB16A

- ADDRA=1
- ADDRA10=1
- ADDRA11=1
- ADDRA12=1
- ADDRA13=1
- ADDRA4=1
- ADDRA5=1
- ADDRA6=1
- ADDRA7=1
- ADDRA8=1
- ADDRA9=1
- CLKA=1
- DIA=1
- DOA=1
- DOA0=1
- DOA1=1
- DOA10=1
- DOA11=1
- DOA12=1
- DOA13=1
- DOA14=1
- DOA15=1
- DOA2=1
- DOA3=1
- DOA4=1
- DOA5=1
- DOA6=1
- DOA7=1
- DOA8=1
- DOA9=1
- DOPA0=1
- DOPA1=1
- ENA=1
- SSRA=1
- WEA=1

SLICEL

- BX=20
- BY=7
- CE=7
- CIN=16
- CLK=38
- COUT=16
- F1=51
- F2=51
- F3=46
- F4=16
- G1=50
- G2=49
- G3=49
- G4=10
- SR=30
- X=20
- XQ=29
- Y=19
- YQ=29

SLICEL_CYMUXF

- 0=22
- 1=22
- OUT=22
- S0=22

SLICEL_CYMUXG

- 0=16
- 1=16
- OUT=16
- S0=16

SLICEL_F

- A1=49
- A2=51
- A3=46
- A4=16
- D=51

SLICEL_F5MUX

- F=9
- G=9
- OUT=9
- S0=9

SLICEL_FFX

- CE=5
- CK=29
- D=29
- Q=29
- SR=24

SLICEL_FFY

- CE=7
- CK=29
- D=29
- Q=29
- SR=21

SLICEL_G

- A1=49
- A2=49
- A3=49
- A4=10
- D=52

SLICEL_GNDF

- 0=14

SLICEL_GNDG

- 0=9

SLICEL_XORF

- 0=17
- 1=17
- O=17

SLICEL_XORG

- 0=20
- 1=20
- O=20

SLICEM

- ALTDIG=8
- BX=26
- BY=34
- BYINVOUT=8
- BYOUT=8
- CLK=34
- DIG=8
- F1=34
- F2=34
- F3=34
- F4=34
- F5=16
- FXINA=8
- FXINB=8
- G1=34
- G2=34
- G3=34
- G4=34
- SLICEWE1=16
- SR=34
- X=8
- XQ=10
- Y=8
- YQ=16

SLICEM_BYINVOUTUSED

- 0=8
- OUT=8

SLICEM_BYOUTUSED

- 0=8
- OUT=8

SLICEM_DIGUSED

- 0=8
- OUT=8

SLICEM_F

- A1=34
- A2=34
- A3=34
- A4=34
- D=34
- DI=34
- WF1=34
- WF2=34
- WF3=34
- WF4=34
- WS=34

SLICEM_F5MUX

- F=26
- G=26
- OUT=26
- S0=26

SLICEM_F6MUX

- 0=8
- 1=8
- OUT=8
- S0=8

SLICEM_FFX

- CK=10
- D=10
- Q=10

SLICEM_FFY

- CK=16
- D=16
- Q=16

SLICEM_G

- A1=34
- A2=34
- A3=34
- A4=34
- D=34
- DI=34
- WG1=34
- WG2=34
- WG3=34
- WG4=34
- WS=34

SLICEM_WSGEN

- CK=34
- WE=34
- WE0=26
- WE1=16
- WSF=34
- WSG=34

Tool Usage
Command Line History

- xst -intstyle ise -ifn <ise_file>
- xst -intstyle ise -ifn <ise_file>
- xst -intstyle ise -ifn <ise_file>
- ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-5 <fname>.ngc <fname>.ngd
- map -intstyle ise -p xc3s500e-fg320-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
- par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
- trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
- bitgen -intstyle ise -f <fname>.ut <fname>.ncd
- fuse

Software Quality
Run Statistics
Program Name | Runs Started | Runs Finished | Errors | Fatal Errors | Internal Errors | Exceptions | Core Dumps
bitgen | 3 | 3 | 0 | 0 | 0 | 0 | 0
elfcheck | 12 | 12 | 0 | 0 | 0 | 0 | 0
libgen | 3 | 3 | 0 | 0 | 0 | 0 | 0
map | 3 | 3 | 0 | 0 | 0 | 0 | 0
ngcbuild | 17 | 17 | 0 | 0 | 0 | 0 | 0
ngdbuild | 3 | 3 | 0 | 0 | 0 | 0 | 0
par | 3 | 3 | 0 | 0 | 0 | 0 | 0
platgen | 3 | 2 | 0 | 0 | 0 | 0 | 0
simgen | 5 | 5 | 0 | 0 | 0 | 0 | 0
trce | 3 | 3 | 0 | 0 | 0 | 0 | 0
xps | 1 | 1 | 0 | 0 | 0 | 0 | 0
xst | 55 | 55 | 0 | 0 | 0 | 0 | 0

Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 | PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML | PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) | PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values | PROP_SelectedInstanceHierarchicalPath=/test_pico
PROP_Simulator=ISim (VHDL/Verilog) | PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL | PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor | PROP_intProjectCreationTimestamp=2017-03-03T10:59:35
PROP_intWbtProjectID=8CF5C57157374EE4BA1DEE9D3BC9694D | PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same | PROP_intWorkingDirUsed=No
PROP_selectedSimRootSourceNode_behav=work.test_pico | PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=false | PROP_DevFamily=Spartan3E
PROP_DevDevice=xc3s500e | PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=fg320 | PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-5 | PROP_PreferredLanguage=Verilog
FILE_UCF=1 | FILE_VERILOG=4

Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 | NGDBUILD_NUM_FD=40 | NGDBUILD_NUM_FDE=2 | NGDBUILD_NUM_FDR=30
NGDBUILD_NUM_FDRE=8 | NGDBUILD_NUM_FDRSE=10 | NGDBUILD_NUM_FDS=2 | NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=9 | NGDBUILD_NUM_INV=4 | NGDBUILD_NUM_LUT1=2 | NGDBUILD_NUM_LUT2=5
NGDBUILD_NUM_LUT3=69 | NGDBUILD_NUM_LUT4=33 | NGDBUILD_NUM_MUXCY=39 | NGDBUILD_NUM_MUXF5=9
NGDBUILD_NUM_OBUF=8 | NGDBUILD_NUM_RAM16X1D=8 | NGDBUILD_NUM_RAM32X1S=10 | NGDBUILD_NUM_RAM64X1S=8
NGDBUILD_NUM_RAMB16_S18=1 | NGDBUILD_NUM_VCC=1 | NGDBUILD_NUM_XORCY=37
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 | NGDBUILD_NUM_FD=40 | NGDBUILD_NUM_FDE=2 | NGDBUILD_NUM_FDR=30
NGDBUILD_NUM_FDRE=8 | NGDBUILD_NUM_FDRSE=10 | NGDBUILD_NUM_FDS=2 | NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=9 | NGDBUILD_NUM_IBUFG=1 | NGDBUILD_NUM_INV=4 | NGDBUILD_NUM_LUT1=2
NGDBUILD_NUM_LUT2=5 | NGDBUILD_NUM_LUT3=69 | NGDBUILD_NUM_LUT4=33 | NGDBUILD_NUM_MUXCY=39
NGDBUILD_NUM_MUXF5=9 | NGDBUILD_NUM_OBUF=8 | NGDBUILD_NUM_RAM32X1S=10 | NGDBUILD_NUM_RAM64X1S=8
NGDBUILD_NUM_RAMB16_S18=1 | NGDBUILD_NUM_VCC=1 | NGDBUILD_NUM_XORCY=37

XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj | -ifmt=mixed | -ofn=<design_top> | -ofmt=NGC
-p=xc3s500e-5-fg320 | -top=<design_top> | -opt_mode=Speed | -opt_level=1
-iuc=NO | -keep_hierarchy=No | -netlist_hierarchy=As_Optimized | -rtlview=Yes
-glob_opt=AllClockNets | -read_cores=YES | -write_timing_constraints=NO | -cross_clock_analysis=NO
-bus_delimiter=<> | -slice_utilization_ratio=100 | -bram_utilization_ratio=100 | -verilog2001=YES
-fsm_extract=YES | -fsm_encoding=Auto | -safe_implementation=No | -fsm_style=LUT
-ram_extract=Yes | -ram_style=Auto | -rom_extract=Yes | -shreg_extract=YES
-rom_style=Auto | -auto_bram_packing=NO | -resource_sharing=YES | -async_to_sync=NO
-mult_style=Auto | -iobuf=YES | -max_fanout=100000 | -bufg=24
-register_duplication=YES | -register_balancing=No | -optimize_primitives=NO | -use_clock_enable=Yes
-use_sync_set=Yes | -use_sync_reset=Yes | -iob=Auto | -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5

ISim Statistics
Xilinx HDL Libraries Used=unisims_ver
Fuse Resource Usage=670 ms, 31208 KB