`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:04:00 02/16/2015
// Design Name:   filtre
// Module Name:   C:/Users/Emrah/Desktop/SFS/FIR_Ornek/test11.v
// Project Name:  FIR_Ornek
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: filtre
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test11;

	// Inputs
	reg clk;
	reg [7:0] giris;

	// Outputs
	wire [7:0] cikis;

	// Instantiate the Unit Under Test (UUT)
	filtre uut (
		.clk(clk), 
		.giris(giris), 
		.cikis(cikis)
	);
	integer giris_dosyasi;
	integer cikis_dosyasi;
	integer scanning;
	integer ornek;
	initial begin
		// Initialize Inputs
		clk = 0;
		giris = 0;
		giris_dosyasi= $fopen("giris_data.txt","r");
		cikis_dosyasi= $fopen("cikis_data.txt","w");
		// Wait 100 ns for global reset to finish
		 #100;
       for(ornek=1; ornek<=1000;ornek=ornek+1)begin
				scanning= $fscanf(giris_dosyasi,"%h\n", giris);
				#10000;
				$fdisplay(cikis_dosyasi,"%h",cikis);
		 end
		 $fclose(giris_dosyasi);
		 $fclose(cikis_dosyasi);
		// Add stimulus here
		end
		
		always begin
		#5000;
		clk = ~clk;
		end

      
endmodule

