`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:19:45 02/09/2015 
// Design Name: 
// Module Name:    filtre 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module filtre(
    input clk,
    input [7:0] giris,
    output [7:0] cikis
    );

wire signed [7:0] c0=8'hFE;
wire signed [7:0] c1=8'h03;
wire signed [7:0] c2=8'h01;
wire signed [7:0] c3=8'hF7;
wire signed [7:0] c4=8'h09;
wire signed [7:0] c5=8'h1E;
wire signed [7:0] c6=8'h1E;
wire signed [7:0] c7=8'h09;
wire signed [7:0] c8=8'hF7;
wire signed [7:0] c9=8'h01;
wire signed [7:0] c10=8'h03;
wire signed [7:0] c11=8'hFE;

reg signed [7:0] i0 = 8'h00;
reg signed [7:0] i1 = 8'h00;
reg signed [7:0] i2 = 8'h00;
reg signed [7:0] i3 = 8'h00;
reg signed [7:0] i4 = 8'h00;
reg signed [7:0] i5 = 8'h00;
reg signed [7:0] i6 = 8'h00;
reg signed [7:0] i7 = 8'h00;
reg signed [7:0] i8 = 8'h00;
reg signed [7:0] i9 = 8'h00;
reg signed [7:0] i10 = 8'h00;
reg signed [7:0] i11 = 8'h00;

wire signed [7:0] m0;
wire signed [7:0] m1;
wire signed [7:0] m2;
wire signed [7:0] m3;
wire signed [7:0] m4;
wire signed [7:0] m5;
wire signed [7:0] m6;
wire signed [7:0] m7;
wire signed [7:0] m8;
wire signed [7:0] m9;
wire signed [7:0] m10;
wire signed [7:0] m11;
wire signed [7:0] m12;

carpici carp0	(giris, c0, m0);
carpici carp1	(i1, c1, m1);
carpici carp2	(i2, c2, m2);
carpici carp3	(i3, c3, m3);
carpici carp4	(i4, c4, m4);
carpici carp5	(i5, c5, m5);
carpici carp6	(i6, c6, m6);
carpici carp7	(i7, c7, m7);
carpici carp8	(i8, c8, m8);
carpici carp9	(i9, c9, m9);
carpici carp10	(i10, c10, m10);
carpici carp11	(i11, c11, m11);

always @(posedge clk) begin
	i1<=giris;
	i2<=i1;
	i3<=i2;
	i4<=i3;
	i5<=i4;
	i6<=i5;
	i7<=i6;
	i8<=i7;
	i9<=i8;
	i10<=i9;
	i11<=i10;
end

assign cikis = m0 + m1 + m2 + m3 + m4 + m5 + m6 + m7 + m8 + m9 + m10 + m11;

endmodule
