`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:08:54 03/03/2017 
// Design Name: 
// Module Name:    top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module top(
    input [7:0] sw,
	 input reset,
    output reg [7:0] leds,
    input clk
    );

wire [9:0] address;
wire [17:0] instruction;
wire [7:0] port_id;
wire write_strobe;
wire [7:0] out_port;
wire read_strobe;
reg [7:0] in_port;
wire interrupt;
wire interrupt_ack;


kcpsm3 picoblaze (
    .address(address), 
    .instruction(instruction), 
    .port_id(port_id), 
    .write_strobe(write_strobe), 
    .out_port(out_port), 
    .read_strobe(read_strobe), 
    .in_port(in_port), 
    .interrupt(1'b0), 
    .interrupt_ack(interrupt_ack), 
    .reset(reset), 
    .clk(clk)
    );

leds prog_rom (
    .address(address), 
    .instruction(instruction), 
    .clk(clk)
    );

always @(posedge clk)
begin
//	if(read_strobe==1)
//	begin
//		in_port<=sw;
//	end
	in_port<=sw;
	leds<=out_port;
end

endmodule
