`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:51:26 03/24/2017
// Design Name:   bram_pico
// Module Name:   C:/Users/EMRAH/Desktop/170324/BRAM/Bram_Pico/test_bram.v
// Project Name:  Bram_Pico
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: bram_pico
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_bram;

	// Inputs
	reg clk;
	reg reset;

	// Instantiate the Unit Under Test (UUT)
	bram_pico uut (
		.clk(clk), 
		.reset(reset)
	);
	
	always
	begin
		#10;
		clk=~clk;
	end

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

