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<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
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<section name="Project Statistics" visible="true">
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<property name="PROP_SynthTopFile" value="changed" type="process"/>
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<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
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<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.test_bram" type="process"/>
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